Examples modified

4 files changed, 7 insertions, 3 deletions

diff --git a/Example/combinational_logic/full_adder/full_adder_sl.vhdl b/Example/combinational_logic/full_adder/full_adder_sl.vhdl
index e830563..99976ba 100644
--- a/Example/combinational_logic/full_adder/full_adder_sl.vhdl
+++ b/Example/combinational_logic/full_adder/full_adder_sl.vhdl
@@ -1,3 +1,4 @@
+-- This file uses only std_logic(sl) variable types
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -16,4 +17,4 @@ architecture rtl of full_adder_sl is
 begin
   o_sum   <= i_bit1 xor i_bit2 xor i_bit3;
   o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1);
-end rtl;
\ No newline at end of file
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl
index 7de9c1b..cd7b5f3 100644
--- a/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl
+++ b/Example/combinational_logic/full_adder/full_adder_sl_slv.vhdl
@@ -1,3 +1,4 @@
+--This file uses combination of std_logic(sl) and std_logic_vector(slv) variable types
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -16,4 +17,4 @@ architecture rtl of full_adder_sl_slv is
 begin
   o_sum   <= i_bit1 xor i_bit2 xor i_bit3(0);
   o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1);
-end rtl;
\ No newline at end of file
+end rtl;
diff --git a/Example/combinational_logic/full_adder/full_adder_slv.vhdl b/Example/combinational_logic/full_adder/full_adder_slv.vhdl
index a0495f0..8dccce9 100644
--- a/Example/combinational_logic/full_adder/full_adder_slv.vhdl
+++ b/Example/combinational_logic/full_adder/full_adder_slv.vhdl
@@ -1,3 +1,4 @@
+--This file uses only std_logic_vector(slv) variable type
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/Example/combinational_logic/full_adder/full_adder_structural.vhdl b/Example/combinational_logic/full_adder/full_adder_structural.vhdl
index eb06a3d..ad13a2d 100644
--- a/Example/combinational_logic/full_adder/full_adder_structural.vhdl
+++ b/Example/combinational_logic/full_adder/full_adder_structural.vhdl
@@ -1,3 +1,4 @@
+--This file uses structural style and uses only std_logic variable type
 library ieee;
 use ieee.std_logic_1164.all;
 
@@ -84,4 +85,4 @@ u4 : andgate port map(a,b,c3);
 u5 : orgate port map(c2,c3,carry);
 
 
-end structural;
\ No newline at end of file
+end structural;