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authorsaurabhb172019-12-30 12:37:57 +0530
committerGitHub2019-12-30 12:37:57 +0530
commit9faa3ee18b0fe7ec50399b06280a5247658c3e9c (patch)
tree0ff4c4791a65364e3b93c91f56342569c7f7a7c9 /Example/combinational_logic/counter/updown_counter.vhdl
parent04d9c666b4bb19936dfa469f536fb38107e631eb (diff)
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Merge pull request #35 from saurabhb17/master
Changes for 1.1.3 version release
Diffstat (limited to 'Example/combinational_logic/counter/updown_counter.vhdl')
-rw-r--r--Example/combinational_logic/counter/updown_counter.vhdl32
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diff --git a/Example/combinational_logic/counter/updown_counter.vhdl b/Example/combinational_logic/counter/updown_counter.vhdl
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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+entity updown_counter is
+ Port ( clk: in std_logic;
+ reset: in std_logic;
+ up_down: in std_logic;
+ counter: out std_logic_vector(3 downto 0)
+ );
+end updown_counter;
+
+architecture Behavioral of updown_counter is
+signal tmp: std_logic_vector(3 downto 0);
+begin
+
+process(clk,reset)
+begin
+ if(reset='1') then
+ tmp <= "0000";
+ elsif(clk'event and clk='1') then
+ if(up_down='1') then
+ tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)-1), tmp'length));
+ else
+ tmp <= std_logic_vector(to_unsigned(to_integer(unsigned(tmp)+1), tmp'length));
+ end if;
+ end if;
+end process;
+ counter <= std_logic_vector(tmp);
+
+end Behavioral; \ No newline at end of file