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author | rahul | 2019-10-22 11:27:47 +0530 |
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committer | rahul | 2019-10-22 11:27:47 +0530 |
commit | 76241122c16990ee003df89391c85ee478ea0dca (patch) | |
tree | 8055abb97cb298fa4dde4e11a3759ff2ea7358f0 /Example/bin_to_gray | |
parent | 0b2a123b6ea6c3d09fae9fb054849432373794cf (diff) | |
download | nghdl-76241122c16990ee003df89391c85ee478ea0dca.tar.gz nghdl-76241122c16990ee003df89391c85ee478ea0dca.tar.bz2 nghdl-76241122c16990ee003df89391c85ee478ea0dca.zip |
Examples
Diffstat (limited to 'Example/bin_to_gray')
-rw-r--r-- | Example/bin_to_gray/bin_to_gray.vhdl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Example/bin_to_gray/bin_to_gray.vhdl b/Example/bin_to_gray/bin_to_gray.vhdl index 542f7ec..d6045e8 100644 --- a/Example/bin_to_gray/bin_to_gray.vhdl +++ b/Example/bin_to_gray/bin_to_gray.vhdl @@ -3,8 +3,8 @@ USE ieee.std_logic_1164.ALL; entity bin_to_gray is port( - bin : in std_logic_vector(3 downto 0); -- binary input - G : out std_logic_vector(3 downto 0) -- gray code output + bin : in std_logic_vector(3 downto 0); + G : out std_logic_vector(3 downto 0) ); end bin_to_gray; |