added examples and modified server

1 files changed, 3 insertions, 3 deletions

diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
index 9d65b8d..7eb3c67 100644
--- a/Example/2-bit-inverter/inverter.vhdl
+++ b/Example/2-bit-inverter/inverter.vhdl
@@ -2,13 +2,13 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity inverter is
-    port ( i: in std_logic_vector(1 downto 0);
-           o: out std_logic_vector(1 downto 0));
+    port ( i: in std_logic_vector(0 downto 0);
+           o: out std_logic_vector(0 downto 0));
 end inverter;
 
 architecture inverter_beh of inverter is
 begin
     o <= not i;
-end architecture;
+end inverter_beh;