Subject: Added example

Description: Added two example xor and 2-bit inverter

2 files changed, 50 insertions, 0 deletions

diff --git a/Example/2-bit-inverter/2-bit-inverter.cir b/Example/2-bit-inverter/2-bit-inverter.cir
new file mode 100644
index 0000000..71794b2
--- /dev/null
+++ b/Example/2-bit-inverter/2-bit-inverter.cir
@@ -0,0 +1,36 @@
+* analysis type *
+.tran 1n 100n
+*
+* input sources *
+v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 2.0 20n 0 20.1n 2.0 25n 2.0 25.1n 2.0 30n 2.0 30.1n 2.0
+               + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
+
+v2 200 0 DC PWL ( 0n 2.0 5n 2.0 5.1n 0.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 0.0 20n 0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 2.0 30.1n 2.0
+               + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
+
+* resistors to ground *
+r1 100 0 1k
+r2 200 0 1k
+
+rload1 300 0 10k
+rload2 400 0 10k
+*
+* adc_bridge blocks *
+aconverter1 [100 200]  [1 2] adc_bridge1
+
+.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
++ rise_delay =1.0e-12 fall_delay =1.0e-12)
+
+ainverter [1 2] [10 20]  inv1
+
+.model inv1 inverter(rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time=90e-9)
+
+
+aconverter2 [10 20] [30 40] dac_bridge1
+
+.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
+
+.end
+ 
+
diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
new file mode 100644
index 0000000..9d65b8d
--- /dev/null
+++ b/Example/2-bit-inverter/inverter.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter is
+    port ( i: in std_logic_vector(1 downto 0);
+           o: out std_logic_vector(1 downto 0));
+end inverter;
+
+architecture inverter_beh of inverter is
+begin
+    o <= not i;
+end architecture;
+
+