Subject: Added example

Description: Added two example xor and 2-bit inverter

1 files changed, 14 insertions, 0 deletions

diff --git a/Example/2-bit-inverter/inverter.vhdl b/Example/2-bit-inverter/inverter.vhdl
new file mode 100644
index 0000000..9d65b8d
--- /dev/null
+++ b/Example/2-bit-inverter/inverter.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter is
+    port ( i: in std_logic_vector(1 downto 0);
+           o: out std_logic_vector(1 downto 0));
+end inverter;
+
+architecture inverter_beh of inverter is
+begin
+    o <= not i;
+end architecture;
+
+