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author | rahul | 2019-10-24 10:31:06 +0530 |
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committer | rahul | 2019-10-24 10:31:06 +0530 |
commit | 1782d61c433157397a21b61a30d4f478ea7eb623 (patch) | |
tree | c533f333a203d7a1c0a32f6fb681ce46ca4b0211 | |
parent | d472bf02bbb957dafa1227277b0421f52c9d7375 (diff) | |
download | nghdl-1782d61c433157397a21b61a30d4f478ea7eb623.tar.gz nghdl-1782d61c433157397a21b61a30d4f478ea7eb623.tar.bz2 nghdl-1782d61c433157397a21b61a30d4f478ea7eb623.zip |
removed trial_xor example
-rw-r--r-- | Example/esim_trial_xor/esim_trial_xor.vhdl | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/Example/esim_trial_xor/esim_trial_xor.vhdl b/Example/esim_trial_xor/esim_trial_xor.vhdl deleted file mode 100644 index ff9190c..0000000 --- a/Example/esim_trial_xor/esim_trial_xor.vhdl +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity esim_trial_xor is - port (a : in std_logic_vector(0 downto 0); - b : in std_logic_vector(0 downto 0); - c : out std_logic_vector(0 downto 0)); - end esim_trial_xor; - - architecture rtl of esim_trial_xor is - begin - - c <= a xor b; - - end rtl; |