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author | fahim | 2015-03-30 12:56:06 +0530 |
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committer | fahim | 2015-03-30 12:56:06 +0530 |
commit | 880869a2aaf695201a833d5fea65d7b9186a0950 (patch) | |
tree | 991b1c9666244f570115894a6b21f4ac14c9c6e6 | |
parent | 0975f7e91106f152d7367a2155b4272e9e9f15c9 (diff) | |
download | nghdl-880869a2aaf695201a833d5fea65d7b9186a0950.tar.gz nghdl-880869a2aaf695201a833d5fea65d7b9186a0950.tar.bz2 nghdl-880869a2aaf695201a833d5fea65d7b9186a0950.zip |
Subject: Make few changes in readme file
Description: Rephrase few statement
-rw-r--r-- | readme.md | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -42,10 +42,10 @@ for that model it will actually call the ghdl to get the result. ##LIMITATION: 1. You can use only one output port in your file. 2. All the port should be std_logic_vector only. -3. We can use only one code model of such type in our netlist. +3. We can use only one instance of code model in netlist. ##FUTURE WORK 1. Make changes to have more than one output. -2. Making changes to include use of more than one code models. -3. Interfacing it with FreeEDA formely known as Oscad so that we can use it in our schematic. +2. Making changes to include use of more than one instance of code models. +3. Interfacing it with eSim formely known as Oscad so that we can use it in our schematic. |