# This is the template file for creating symbols with tragesym # every line starting with '#' is a comment line. [options] # rotate_labels rotates the pintext of top and bottom pins # wordswap swaps labels if the pin is on the right side an looks like this: # "PB1 (CLK)" wordswap=yes rotate_labels=yes sort_labels=no generate_pinseq=yes sym_width=2800 pinwidthvertikal=400 pinwidthhorizontal=400 [geda_attr] # name will be printed in the top of the symbol # if you have a device with slots, you'll have to use slot= and slotdef= # use comment= if there are special information you want to add version=20030525 name=EP2C20-F484-IO3 device=EP2C20-F484 refdes=U? footprint=FG484 description=EP2C20 Cyclone II FPGA documentation=http://www.altera.com author=mettus numslots=0 #slot=1 #slotdef=1: #slotdef=2: #slotdef=3: #slotdef=4: #comment= #comment= #comment= [pins] # tabseparated list of pin descriptions # pinnr is the physical number of the pin # seq is the pinseq= attribute, leave it blank if it doesn't matter # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) # style can be (line,dot,clk,dotclk,none). none if only want to add a net # posit. can be (l,r,t,b) or empty for nets # net specifies the name of the Vcc or GND name # label represents the pinlabel. # negation lines can be added with _Q_ # if you want to add a "_" or "\" use "\_" and "\\" as escape sequences #----------------------------------------------------- #pinnr seq type style posit. net label #----------------------------------------------------- D12 clk clk r CLK10/_LVDSCLK5N_ E12 clk clk r CLK11/LVDSCLK5P B11 io line l IO/_LVDS44N_ A11 io line l IO/LVDS44P E11 io line l IO/_LVDS43N_ D11 io line l IO/LVDS43P H11 io line l IO/_LVDS42N_ G11 io line l IO/LVDS42P B10 io line l IO/_LVDS41N_ A10 io line l IO/LVDS41P F11 io line l IO/_LVDS40N_ F10 io line l IO/LVDS40P C10 io line l IO/VREFB3N0 B9 io line l IO/_LVDS39N_ A9 io line l IO/LVDS39P H10 io line l IO/_LVDS38N_ H9 io line l IO/LVDS38P E9 io line l IO/_LVDS37N_ D9 io line l IO/LVDS37P B8 io line l IO/_LVDS36N_ A8 io line l IO/LVDS36P B7 io line l IO/_LVDS35N_ A7 io line l IO/LVDS35P F9 io line l IO/_LVDS34N_ E8 io line l IO/LVDS34P D8 io line l IO/_LVDS33N_ C9 io line l IO/LVDS33P D7 io line l IO F8 io line l IO/_LVDS32N_ G8 io line l IO/LVDS32P H8 io line l IO C7 io line l IO/VREFB3N1 E7 io line l IO G7 io line l IO/_LVDS31N_ H7 io line l IO/LVDS31P B6 io line l IO/_LVDS30N_ A6 io line l IO/LVDS30P B5 io line l IO/_LVDS29N_ A5 io line l IO/LVDS29P B4 io line l IO/_LVDS28N_ A4 io line l IO/LVDS28P A3 io line l IO/LVDS27P B3 io line l IO/_LVDS27N_/_DEV\_CLRn_