From 959904c4b65d13328e31b36c9ccee404ac988e09 Mon Sep 17 00:00:00 2001
From: matt
Date: Sat, 18 Oct 2008 23:33:12 +0000
Subject: added in mux for DACs

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9807 221aa14e-8319-0410-a670-987f0aec2ac5
---
 usrp2/firmware/lib/memory_map.h  |  5 +++--
 usrp2/fpga/sdr_lib/dsp_core_tx.v | 20 ++++++++++++++++----
 2 files changed, 19 insertions(+), 6 deletions(-)

(limited to 'usrp2')

diff --git a/usrp2/firmware/lib/memory_map.h b/usrp2/firmware/lib/memory_map.h
index a7d38a15c..740bf47fa 100644
--- a/usrp2/firmware/lib/memory_map.h
+++ b/usrp2/firmware/lib/memory_map.h
@@ -407,11 +407,12 @@ typedef struct {
    *   1   DUC 0 Q
    *   2   DUC 1 I
    *   3   DUC 1 Q
-   *
+   *   F   All Zeros
+   *   
    * The default value is 0x10
    * </pre>
    */
-  //volatile uint32_t	tx_mux;		// FIXME this register is currently unimplemented
+  volatile uint32_t	tx_mux;		// FIXME this register is currently unimplemented
 
 } dsp_tx_regs_t;
   
diff --git a/usrp2/fpga/sdr_lib/dsp_core_tx.v b/usrp2/fpga/sdr_lib/dsp_core_tx.v
index c311e79f1..535f2003e 100644
--- a/usrp2/fpga/sdr_lib/dsp_core_tx.v
+++ b/usrp2/fpga/sdr_lib/dsp_core_tx.v
@@ -19,7 +19,7 @@ module dsp_core_tx
    wire [31:0] phase_inc;
    reg [31:0]  phase;
    wire [7:0]  interp_rate;
-
+   wire [3:0]  dacmux_a, dacmux_b;
    wire        enable_hb1, enable_hb2;
 
    setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
@@ -34,6 +34,10 @@ module dsp_core_tx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
 
+   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+4)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({dacmux_b,dacmux_a}),.changed());
+
    // Strobes are all now delayed by 1 cycle for timing reasons
    wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
    reg 	       strobe_cic = 1;
@@ -122,11 +126,19 @@ module dsp_core_tx
       );
    
    always @(posedge clk)
-     dac_a <= prod_i[28:13];
+     case(dacmux_a)
+       0 : dac_a <= prod_i[28:13];
+       1 : dac_a <= prod_q[28:13];
+       default : dac_a <= 0;
+     endcase // case(dacmux_a)
    
    always @(posedge clk)
-     dac_b <= prod_q[28:13];
-
+     case(dacmux_b)
+       0 : dac_b <= prod_i[28:13];
+       1 : dac_b <= prod_q[28:13];
+       default : dac_b <= 0;
+     endcase // case(dacmux_b)
+   
    assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
 
 endmodule // dsp_core
-- 
cgit