From a3e0ae23c39b34c5f652c8ae830e6fe33342817c Mon Sep 17 00:00:00 2001
From: matt
Date: Wed, 8 Oct 2008 06:29:43 +0000
Subject: moved to appropriate places

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9747 221aa14e-8319-0410-a670-987f0aec2ac5
---
 usrp2/fpga/control_lib/extram_interface.v | 53 -------------------------------
 usrp2/fpga/extram/extram_interface.v      | 53 +++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+), 53 deletions(-)
 delete mode 100644 usrp2/fpga/control_lib/extram_interface.v
 create mode 100644 usrp2/fpga/extram/extram_interface.v

(limited to 'usrp2/fpga')

diff --git a/usrp2/fpga/control_lib/extram_interface.v b/usrp2/fpga/control_lib/extram_interface.v
deleted file mode 100644
index 7554592ba..000000000
--- a/usrp2/fpga/control_lib/extram_interface.v
+++ /dev/null
@@ -1,53 +0,0 @@
-
-// Temporary buffer pool storage, mostly useful for pre-generated data streams or
-//   for making more space to juggle packets in case of eth frames coming out of order
-
-module extram_interface
-  (input clk, input rst,
-   input set_stb, input [7:0] set_addr, input [31:0] set_data,
-   
-   // Buffer pool interfaces
-   input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
-   input rd_sop_i, input rd_eop_i,
-   output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
-   input wr_ready_i, input wr_full_i,
-   
-   // RAM Interface
-   inout [17:0] RAM_D,
-   output [18:0] RAM_A,
-   output RAM_CE1n,
-   output RAM_CENn,
-   input RAM_CLK,
-   output RAM_WEn,
-   output RAM_OEn,
-   output RAM_LDn );
-
-   // Command format --
-   //    Read/_Write , start address[17:0]
-   wire [18:0] cmd_in;
-   wire        cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd;
-   wire        empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd;
-   
-   // Dummy logic
-   assign RAM_OEn = 1;
-   
-   setting_reg #(.my_addr(0)) 
-     sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-		 .in(set_data),.out(cmd_in),.changed(cmd_stb));
-   
-   reg 	  cmd_stb_d1;
-   always @(posedge clk) cmd_stb_d1 <= cmd_stb;
-   assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1;
-   assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1;   
-
-   shortfifo #(.WIDTH(19)) wr_cmd_fifo
-     (.clk(clk),.rst(rst),.clear(1'b0),
-      .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd),
-      .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) );
-
-   shortfifo #(.WIDTH(19)) rd_cmd_fifo
-     (.clk(clk),.rst(rst),.clear(1'b0),
-      .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd),
-      .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) );
-
-endmodule // extram_interface
diff --git a/usrp2/fpga/extram/extram_interface.v b/usrp2/fpga/extram/extram_interface.v
new file mode 100644
index 000000000..7554592ba
--- /dev/null
+++ b/usrp2/fpga/extram/extram_interface.v
@@ -0,0 +1,53 @@
+
+// Temporary buffer pool storage, mostly useful for pre-generated data streams or
+//   for making more space to juggle packets in case of eth frames coming out of order
+
+module extram_interface
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+   
+   // Buffer pool interfaces
+   input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
+   input rd_sop_i, input rd_eop_i,
+   output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
+   input wr_ready_i, input wr_full_i,
+   
+   // RAM Interface
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   input RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn );
+
+   // Command format --
+   //    Read/_Write , start address[17:0]
+   wire [18:0] cmd_in;
+   wire        cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd;
+   wire        empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd;
+   
+   // Dummy logic
+   assign RAM_OEn = 1;
+   
+   setting_reg #(.my_addr(0)) 
+     sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+		 .in(set_data),.out(cmd_in),.changed(cmd_stb));
+   
+   reg 	  cmd_stb_d1;
+   always @(posedge clk) cmd_stb_d1 <= cmd_stb;
+   assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1;
+   assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1;   
+
+   shortfifo #(.WIDTH(19)) wr_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd),
+      .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) );
+
+   shortfifo #(.WIDTH(19)) rd_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd),
+      .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) );
+
+endmodule // extram_interface
-- 
cgit