From 7eea883c377f64862a4d83f1b33a83fdf3cfc392 Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Mon, 31 Aug 2009 12:08:30 -0700 Subject: Merged SVN matt/new_eth r10782:11633 into new_eth * svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz. --- usrp2/fpga/top/u2_rev3/Makefile | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'usrp2/fpga/top/u2_rev3') diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile index c41ce7f77..5d782b610 100644 --- a/usrp2/fpga/top/u2_rev3/Makefile +++ b/usrp2/fpga/top/u2_rev3/Makefile @@ -56,14 +56,16 @@ export SOURCES := \ control_lib/CRC16_D16.v \ control_lib/atr_controller.v \ control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ control_lib/cascadefifo2.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ control_lib/dpram32.v \ control_lib/fifo_2clock.v \ control_lib/fifo_2clock_casc.v \ +control_lib/newfifo/newfifo_2clock.v \ +control_lib/newfifo/cascadefifo_2clock.v \ control_lib/gray2bin.v \ control_lib/gray_send.v \ control_lib/icache.v \ @@ -89,6 +91,22 @@ control_lib/oneshot_2clk.v \ control_lib/sd_spi.v \ control_lib/sd_spi_wb.v \ control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/address_filter.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo36_to_ll8.v \ coregen/fifo_xlnx_2Kx36_2clk.v \ coregen/fifo_xlnx_2Kx36_2clk.xco \ coregen/fifo_xlnx_512x36_2clk.v \ -- cgit From 43dec22f22e9c47b4f908675ac880a05377993fa Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 3 Sep 2009 14:13:44 -0700 Subject: MAC transmit seems to work now. The root cause of the problem was accidentally using the rx_clk in one stage of the fifos on the tx side. --- usrp2/fpga/top/u2_rev3/Makefile | 56 +++++++++++++---------------------------- 1 file changed, 17 insertions(+), 39 deletions(-) (limited to 'usrp2/fpga/top/u2_rev3') diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile index 5d782b610..7847b8c72 100644 --- a/usrp2/fpga/top/u2_rev3/Makefile +++ b/usrp2/fpga/top/u2_rev3/Makefile @@ -56,20 +56,12 @@ export SOURCES := \ control_lib/CRC16_D16.v \ control_lib/atr_controller.v \ control_lib/bin2gray.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/cascadefifo2.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/newfifo/newfifo_2clock.v \ -control_lib/newfifo/cascadefifo_2clock.v \ control_lib/gray2bin.v \ control_lib/gray_send.v \ control_lib/icache.v \ -control_lib/longfifo.v \ control_lib/mux4.v \ control_lib/mux8.v \ control_lib/nsgpio.v \ @@ -78,8 +70,6 @@ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ @@ -101,43 +91,31 @@ simple_gemac/crc.v \ simple_gemac/delay_line.v \ simple_gemac/flow_ctrl_tx.v \ simple_gemac/address_filter.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ simple_gemac/ll8_to_txmac.v \ simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ coregen/fifo_xlnx_2Kx36_2clk.v \ coregen/fifo_xlnx_2Kx36_2clk.xco \ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ -- cgit From 9e05f0770b92f9c85f09e3629f875011e8f1ac24 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 4 Sep 2009 22:23:27 -0700 Subject: Implement Eth flow control using pause frames Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though. --- usrp2/fpga/top/u2_rev3/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'usrp2/fpga/top/u2_rev3') diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile index 7847b8c72..94681f6cd 100644 --- a/usrp2/fpga/top/u2_rev3/Makefile +++ b/usrp2/fpga/top/u2_rev3/Makefile @@ -90,6 +90,7 @@ simple_gemac/simple_gemac_rx.v \ simple_gemac/crc.v \ simple_gemac/delay_line.v \ simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ simple_gemac/address_filter.v \ simple_gemac/ll8_to_txmac.v \ simple_gemac/rxmac_to_ll8.v \ -- cgit