From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
---
 usrp2/fpga/sdr_lib/add2_and_round_reg.v | 16 ----------------
 1 file changed, 16 deletions(-)
 delete mode 100644 usrp2/fpga/sdr_lib/add2_and_round_reg.v

(limited to 'usrp2/fpga/sdr_lib/add2_and_round_reg.v')

diff --git a/usrp2/fpga/sdr_lib/add2_and_round_reg.v b/usrp2/fpga/sdr_lib/add2_and_round_reg.v
deleted file mode 100644
index e7fcbf1a1..000000000
--- a/usrp2/fpga/sdr_lib/add2_and_round_reg.v
+++ /dev/null
@@ -1,16 +0,0 @@
-
-module add2_and_round_reg
-  #(parameter WIDTH=16)
-    (input clk,
-     input [WIDTH-1:0] in1,
-     input [WIDTH-1:0] in2,
-     output reg [WIDTH-1:0] sum);
-
-   wire [WIDTH-1:0] sum_int;
-   
-   add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int));
-
-   always @(posedge clk)
-     sum <= sum_int;
-   
-endmodule // add2_and_round_reg
-- 
cgit