From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
---
 usrp2/fpga/opencores/aemb/sim/cversim | 22 ----------------------
 1 file changed, 22 deletions(-)
 delete mode 100755 usrp2/fpga/opencores/aemb/sim/cversim

(limited to 'usrp2/fpga/opencores/aemb/sim/cversim')

diff --git a/usrp2/fpga/opencores/aemb/sim/cversim b/usrp2/fpga/opencores/aemb/sim/cversim
deleted file mode 100755
index 0dbb7aea1..000000000
--- a/usrp2/fpga/opencores/aemb/sim/cversim
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/sh
-# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
-# $Log: cversim,v $
-# Revision 1.5  2007/12/11 00:44:30  sybreon
-# Modified for AEMB2
-#
-# Revision 1.4  2007/11/30 17:08:30  sybreon
-# Moved simulation kernel into code.
-#
-# Revision 1.3  2007/11/05 10:59:31  sybreon
-# Added random seed for simulation.
-#
-# Revision 1.2  2007/04/12 20:21:33  sybreon
-# Moved testbench into /sim/verilog.
-# Simulation cleanups.
-#
-# Revision 1.1  2007/03/09 17:41:55  sybreon
-# initial import
-#
-RANDOM=$(date +%s)
-echo "parameter randseed = $RANDOM;" > random.v
-cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v
-- 
cgit