From f5fdfe3342750df3092bd0a8d39cb42b4d599012 Mon Sep 17 00:00:00 2001
From: matt
Date: Thu, 22 Jan 2009 18:23:45 +0000
Subject: trial fix for problem when 3 loads with 1 wait state are followed by
 a barrel shift or multiply.  Shawn will let us know if this works.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10290 221aa14e-8319-0410-a670-987f0aec2ac5
---
 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'usrp2/fpga/opencores/aemb/rtl/verilog')

diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
index b3e37c448..a4edf1d90 100644
--- a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
+++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
@@ -149,7 +149,7 @@ module aeMB_ibuf (/*AUTOARG*/
 	rSTALL <= 1'h0;
 	// End of automatics
      end else begin
-	rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);	
+	rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL);	
      end
    
 endmodule // aeMB_ibuf
@@ -189,4 +189,4 @@ endmodule // aeMB_ibuf
  New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
  Fixed various minor data hazard bugs.
  Code compatible with -O0/1/2/3/s generated code.
-*/
\ No newline at end of file
+*/
-- 
cgit