From e0fcbaee124d3e8c4c11bdda662f88e082352058 Mon Sep 17 00:00:00 2001
From: jcorgan
Date: Mon, 8 Sep 2008 01:00:12 +0000
Subject: Merged r9433:9527 from features/gr-usrp2 into trunk.  Adds usrp2 and
 gr-usrp2 top-level components.  Trunk passes distcheck with mb-gcc installed,
 but currently not without them.  The key issue is that when mb-gcc is not
 installed, the build system skips over the usrp2/firmware directory, and the
 firmware include files don't get put into the dist tarball.  But we can't do
 the usual DIST_SUBDIRS method as the firmware is a subpackage.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
---
 usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v | 85 +++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v

(limited to 'usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v')

diff --git a/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
new file mode 100644
index 000000000..7ded9e08b
--- /dev/null
+++ b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
@@ -0,0 +1,85 @@
+
+// RX side of flow control -- when we are running out of RX space, send a PAUSE
+
+module flow_ctrl_rx
+  (input        rst,
+   //host processor
+   input        pause_frame_send_en,
+   input [15:0] pause_quanta_set,
+   input [15:0] fc_hwmark,
+   input [15:0] fc_lwmark,
+   // From MAC_rx_ctrl
+   input        rx_clk,
+   input [15:0] rx_fifo_space,
+   // MAC_tx_ctrl
+   input        tx_clk,
+   output reg   xoff_gen,
+   output reg   xon_gen,
+   input        xoff_gen_complete,
+   input        xon_gen_complete
+   );
+   
+   // ******************************************************************************        
+   // Force our TX to send a PAUSE frame because our RX is nearly full
+   // ******************************************************************************
+
+   reg xon_int, xoff_int;
+   reg [21:0] countdown;
+ 
+   always @(posedge rx_clk or posedge rst)
+     if(rst)
+       begin
+	  xon_int <= 0;
+	  xoff_int <= 0;
+       end
+     else 
+       begin
+	  xon_int <= 0;
+	  xoff_int <= 0;
+	  if(pause_frame_send_en)
+	    if(countdown == 0)
+	      if(rx_fifo_space < fc_lwmark)
+		xoff_int <= 1;
+	      else
+		;
+	    else
+	      if(rx_fifo_space > fc_hwmark)
+		xon_int <= 1;
+       end // else: !if(rst)
+   
+   reg xoff_int_d1, xon_int_d1;
+
+   always @(posedge rx_clk)
+     xon_int_d1 <= xon_int;
+   always @(posedge rx_clk)
+     xoff_int_d1 <= xoff_int;
+   
+   always @ (posedge tx_clk or posedge rst)
+     if (rst)
+       xoff_gen        <=0;
+     else if (xoff_gen_complete)
+       xoff_gen        <=0;
+     else if (xoff_int | xoff_int_d1)
+       xoff_gen        <=1;
+   
+   always @ (posedge tx_clk or posedge rst)
+     if (rst)
+       xon_gen     <=0;
+     else if (xon_gen_complete)
+       xon_gen     <=0;
+     else if (xon_int | xon_int_d1)
+       xon_gen     <=1;                     
+
+   wire [15:0] pq_reduced = pause_quanta_set - 2;
+   
+   always @(posedge tx_clk or posedge rst)
+     if(rst)
+       countdown <= 0;
+     else if(xoff_gen)
+       countdown <= {pq_reduced,6'd0};
+     else if(xon_gen)
+       countdown <= 0;
+     else if(countdown != 0)
+       countdown <= countdown - 1;
+   
+endmodule // flow_ctrl
-- 
cgit