From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
---
 usrp2/fpga/control_lib/WB_SIM.sav | 47 ---------------------------------------
 1 file changed, 47 deletions(-)
 delete mode 100644 usrp2/fpga/control_lib/WB_SIM.sav

(limited to 'usrp2/fpga/control_lib/WB_SIM.sav')

diff --git a/usrp2/fpga/control_lib/WB_SIM.sav b/usrp2/fpga/control_lib/WB_SIM.sav
deleted file mode 100644
index 467cd35ef..000000000
--- a/usrp2/fpga/control_lib/WB_SIM.sav
+++ /dev/null
@@ -1,47 +0,0 @@
-[size] 1400 971
-[pos] -1 -1
-*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-wb_sim.wb_rst
-wb_sim.wb_clk
-@23
-wb_sim.rom_data[47:0]
-@22
-wb_sim.rom_addr[15:0]
-@28
-wb_sim.start
-wb_sim.wb_ack
-@22
-wb_sim.wb_adr[15:0]
-@28
-wb_sim.wb_cyc
-@22
-wb_sim.wb_dat[31:0]
-wb_sim.wb_sel[3:0]
-@28
-wb_sim.wb_stb
-wb_sim.wb_we
-@22
-wb_sim.port_output[31:0]
-@28
-wb_sim.system_control.POR
-wb_sim.system_control.aux_clk
-wb_sim.system_control.clk_fpga
-@29
-wb_sim.system_control.done
-@28
-wb_sim.system_control.dsp_clk
-wb_sim.system_control.fin_del1
-wb_sim.system_control.fin_del2
-wb_sim.system_control.fin_del3
-wb_sim.system_control.fin_ret_aux
-@29
-wb_sim.system_control.fin_ret_fpga
-@28
-wb_sim.system_control.finished
-wb_sim.system_control.reset_out
-wb_sim.system_control.start
-wb_sim.system_control.started
-wb_sim.system_control.wb_clk_o
-wb_sim.system_control.wb_rst_o
-wb_sim.system_control.wb_rst_o_alt
-- 
cgit