From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Sun, 28 Feb 2010 12:47:43 -0800 Subject: Remove usrp1 and usrp2 FPGA files. These are now hosted at: git://ettus.sourcerepo.com/ettus/fpga.git ...under the 'usrp1' and 'usrp2' top-level directories. --- usrp/fpga/sdr_lib/rssi.v | 30 ------------------------------ 1 file changed, 30 deletions(-) delete mode 100644 usrp/fpga/sdr_lib/rssi.v (limited to 'usrp/fpga/sdr_lib/rssi.v') diff --git a/usrp/fpga/sdr_lib/rssi.v b/usrp/fpga/sdr_lib/rssi.v deleted file mode 100644 index e45e2148c..000000000 --- a/usrp/fpga/sdr_lib/rssi.v +++ /dev/null @@ -1,30 +0,0 @@ - - -module rssi (input clock, input reset, input enable, - input [11:0] adc, output [15:0] rssi, output [15:0] over_count); - - wire over_hi = (adc == 12'h7FF); - wire over_lo = (adc == 12'h800); - wire over = over_hi | over_lo; - - reg [25:0] over_count_int; - always @(posedge clock) - if(reset | ~enable) - over_count_int <= #1 26'd0; - else - over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; - - assign over_count = over_count_int[25:10]; - - wire [11:0] abs_adc = adc[11] ? ~adc : adc; - - reg [25:0] rssi_int; - always @(posedge clock) - if(reset | ~enable) - rssi_int <= #1 26'd0; - else - rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; - - assign rssi = rssi_int[25:10]; - -endmodule // rssi -- cgit