From 5d69a524f81f234b3fbc41d49ba18d6f6886baba Mon Sep 17 00:00:00 2001
From: jcorgan
Date: Thu, 3 Aug 2006 04:51:51 +0000
Subject: Houston, we have a trunk.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
---
 usrp/fpga/sdr_lib/clk_divider.v | 43 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100755 usrp/fpga/sdr_lib/clk_divider.v

(limited to 'usrp/fpga/sdr_lib/clk_divider.v')

diff --git a/usrp/fpga/sdr_lib/clk_divider.v b/usrp/fpga/sdr_lib/clk_divider.v
new file mode 100755
index 000000000..a687297b4
--- /dev/null
+++ b/usrp/fpga/sdr_lib/clk_divider.v
@@ -0,0 +1,43 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+//
+
+
+module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
+   reg [7:0] counter;
+   
+   // FIXME maybe should use PLL or switch to double edge version	
+	
+   always @(posedge in_clk or posedge reset)
+     if(reset)
+       counter <= #1 8'd0;
+     else if(counter == 0)
+       counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
+     else
+       counter <= #1 counter-8'd1;
+   
+   always @(posedge in_clk or posedge reset)
+     if(reset)
+       out_clk <= #1 1'b0;
+     else if(counter == 0)
+       out_clk <= #1 ~out_clk;
+   
+endmodule // clk_divider
+
-- 
cgit