From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
---
 usrp/fpga/models/fifo_1k.v | 24 ------------------------
 1 file changed, 24 deletions(-)
 delete mode 100644 usrp/fpga/models/fifo_1k.v

(limited to 'usrp/fpga/models/fifo_1k.v')

diff --git a/usrp/fpga/models/fifo_1k.v b/usrp/fpga/models/fifo_1k.v
deleted file mode 100644
index acfa4d176..000000000
--- a/usrp/fpga/models/fifo_1k.v
+++ /dev/null
@@ -1,24 +0,0 @@
-
-
-module fifo_1k
-  (  input [15:0] data,
-     input 	wrreq,
-     input 	rdreq,
-     input 	rdclk,
-     input 	wrclk,
-     input 	aclr,
-     output [15:0] q,
-     output 	 rdfull,
-     output 	 rdempty,
-     output [9:0] rdusedw,
-     output 	 wrfull,
-     output 	 wrempty,
-     output [9:0]  wrusedw
-     );
-
-fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k 
-  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
-    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
-   
-endmodule // fifo_1k
-   
-- 
cgit