From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
---
 usrp/fpga/megacells/fifo_4kx16_dc.cmp | 31 -------------------------------
 1 file changed, 31 deletions(-)
 delete mode 100755 usrp/fpga/megacells/fifo_4kx16_dc.cmp

(limited to 'usrp/fpga/megacells/fifo_4kx16_dc.cmp')

diff --git a/usrp/fpga/megacells/fifo_4kx16_dc.cmp b/usrp/fpga/megacells/fifo_4kx16_dc.cmp
deleted file mode 100755
index 356de4d62..000000000
--- a/usrp/fpga/megacells/fifo_4kx16_dc.cmp
+++ /dev/null
@@ -1,31 +0,0 @@
---Copyright (C) 1991-2006 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-component fifo_4kx16_dc
-	PORT
-	(
-		aclr		: IN STD_LOGIC  := '0';
-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		rdclk		: IN STD_LOGIC ;
-		rdreq		: IN STD_LOGIC ;
-		wrclk		: IN STD_LOGIC ;
-		wrreq		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-		rdempty		: OUT STD_LOGIC ;
-		rdusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
-		wrfull		: OUT STD_LOGIC ;
-		wrusedw		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
-	);
-end component;
-- 
cgit