From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
---
 usrp/fpga/TODO | 23 -----------------------
 1 file changed, 23 deletions(-)
 delete mode 100644 usrp/fpga/TODO

(limited to 'usrp/fpga/TODO')

diff --git a/usrp/fpga/TODO b/usrp/fpga/TODO
deleted file mode 100644
index 76287c3d4..000000000
--- a/usrp/fpga/TODO
+++ /dev/null
@@ -1,23 +0,0 @@
-
-
-Area Reduction
-==============
-Reduce one or both stages of dec/interp to max rate of 8 instead of 16
-Optimize CICs to minimize registers
-Reduce width of RX CORDIC
-Fix CORDIC wasted logic cells from bad synthesis
-Progressively narrow x,y,z on CORDIC
-16-bit wide FIFOs, split IQ/channels on other side (?)
-
-Enhancements
-============
-Halfband filter in Spartan 3
-Muxing of inputs
-Switch over to newfc
-RAM interface?
-
-Other
-=====
-Capture/Transmit straight samples (no DUC/DDC)
-
-
-- 
cgit