From d470318227a3275fe6cdc7ad6fd293c06da2a963 Mon Sep 17 00:00:00 2001
From: Josh Blum
Date: Thu, 13 Oct 2011 15:29:56 -0700
Subject: uhd: grc xml tweaks + streamer args

---
 gr-uhd/grc/gen_uhd_usrp_blocks.py   | 47 ++++++++++++++++++++-----------------
 gr-uhd/include/gr_uhd_usrp_sink.h   |  2 +-
 gr-uhd/include/gr_uhd_usrp_source.h |  2 +-
 gr-uhd/swig/__init__.py             |  2 ++
 4 files changed, 29 insertions(+), 24 deletions(-)

diff --git a/gr-uhd/grc/gen_uhd_usrp_blocks.py b/gr-uhd/grc/gen_uhd_usrp_blocks.py
index 5a5b2d3ca..7e9841ef9 100644
--- a/gr-uhd/grc/gen_uhd_usrp_blocks.py
+++ b/gr-uhd/grc/gen_uhd_usrp_blocks.py
@@ -28,9 +28,9 @@ MAIN_TMPL = """\
 	<make>uhd.usrp_$(sourk)(
 	device_addr=\$dev_addr,
 	stream_args=uhd.stream_args(
-		cpu_format='\$type',
-		otw_format='\$otw.format',
-		args='\$otw.args',
+		cpu_format="\$type",
+		otw_format=\$otw,
+		args=\$stream_args,
 		channels=range(\$nchan),
 	),
 )
@@ -111,46 +111,49 @@ self.\$(id).set_bandwidth(\$bw$(n), $n)
 			<opt>type:short</opt>
 			<opt>vlen:1</opt>
 		</option>
+		<option>
+			<name>VITA word32</name>
+			<key>item32</key>
+			<opt>type:int</opt>
+			<opt>vlen:1</opt>
+		</option>
 	</param>
 	<param>
 		<name>Wire Format</name>
 		<key>otw</key>
-		<type>enum</type>
+		<type>string</type>
 		<option>
 			<name>Complex int16</name>
 			<key>sc16</key>
-			<opt>format:sc16</opt>
-			<opt>args:</opt>
 		</option>
 		<option>
 			<name>Complex int8</name>
 			<key>sc8</key>
-			<opt>format:sc8</opt>
-			<opt>args:</opt>
 		</option>
 		<option>
 			<name>Real int16</name>
 			<key>s16</key>
-			<opt>format:s16</opt>
-			<opt>args:</opt>
 		</option>
 		<option>
 			<name>Real int8</name>
 			<key>s8</key>
-			<opt>format:s8</opt>
-			<opt>args:</opt>
-		</option>
-		<option>
-			<name>Magnitude int16</name>
-			<key>s16_mag</key>
-			<opt>format:s16</opt>
-			<opt>args:magnitude</opt>
 		</option>
+	</param>
+	<param>
+		<name>Stream args</name>
+		<key>stream_args</key>
+		<value></value>
+		<type>string</type>
+		<hide>
+			\#if \$stream_args()
+				none
+			\#else
+				part
+			\#end if
+		</hide>
 		<option>
-			<name>Magnitude int8</name>
-			<key>s8_mag</key>
-			<opt>format:s8</opt>
-			<opt>args:magnitude</opt>
+			<name>scaler=1024</name>
+			<key>scaler=1024</key>
 		</option>
 	</param>
 	<param>
diff --git a/gr-uhd/include/gr_uhd_usrp_sink.h b/gr-uhd/include/gr_uhd_usrp_sink.h
index 3b4c80879..a74cadab2 100644
--- a/gr-uhd/include/gr_uhd_usrp_sink.h
+++ b/gr-uhd/include/gr_uhd_usrp_sink.h
@@ -38,7 +38,7 @@ namespace uhd{
         }
         std::string cpu_format;
         std::string otw_format;
-        std::string args;
+        device_addr_t args;
         std::vector<size_t> channels;
     };
 }
diff --git a/gr-uhd/include/gr_uhd_usrp_source.h b/gr-uhd/include/gr_uhd_usrp_source.h
index 00747f161..d22d67241 100644
--- a/gr-uhd/include/gr_uhd_usrp_source.h
+++ b/gr-uhd/include/gr_uhd_usrp_source.h
@@ -38,7 +38,7 @@ namespace uhd{
         }
         std::string cpu_format;
         std::string otw_format;
-        std::string args;
+        device_addr_t args;
         std::vector<size_t> channels;
     };
 }
diff --git a/gr-uhd/swig/__init__.py b/gr-uhd/swig/__init__.py
index a50ec82a5..d098a7b8a 100644
--- a/gr-uhd/swig/__init__.py
+++ b/gr-uhd/swig/__init__.py
@@ -66,6 +66,8 @@ def _prepare_uhd_swig():
                 #but what i can do is append the elements individually
                 if key == 'channels':
                     for v in val: self.channels.append(v)
+                elif key == 'args':
+                    self.args = device_addr_t(val)
                 else: setattr(self, key, val)
     setattr(uhd_swig, 'stream_args_t', stream_args_t)
 
-- 
cgit