From cea78cb9b42943fe3e6e0bb598bb8e7cb7caead3 Mon Sep 17 00:00:00 2001
From: eb
Date: Tue, 14 Oct 2008 02:07:19 +0000
Subject: new tx and rx mux registers
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9789 221aa14e-8319-0410-a670-987f0aec2ac5
---
usrp2/firmware/lib/memory_map.h | 58 +++++++++++++++++++++++++++++++++++++++++
usrp2/firmware/lib/u2_init.c | 4 +++
2 files changed, 62 insertions(+)
diff --git a/usrp2/firmware/lib/memory_map.h b/usrp2/firmware/lib/memory_map.h
index aa9951e7a..bbf8165bb 100644
--- a/usrp2/firmware/lib/memory_map.h
+++ b/usrp2/firmware/lib/memory_map.h
@@ -378,6 +378,41 @@ typedef struct {
volatile uint32_t interp_rate;
volatile uint32_t clear_state; // clears out state machine, fifos,
// NOT freq, scale, interp
+ /*!
+ * \brief output mux configuration.
+ *
+ *
+ * 3 2 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------------------------------+-------+-------+-------+-------+
+ * | | DAC1 | DAC0 |
+ * +-------------------------------+-------+-------+-------+-------+
+ *
+ * There are N DUCs (1 now) with complex inputs and outputs.
+ * There are two DACs.
+ *
+ * Each 4-bit DACx field specifies the source for the DAC
+ * Each subfield is coded like this:
+ *
+ * 3 2 1 0
+ * +-------+
+ * | N |
+ * +-------+
+ *
+ * N specifies which DUC output is connected to this DAC.
+ *
+ * N which interp output
+ * --- -------------------
+ * 0 DUC 0 I
+ * 1 DUC 0 Q
+ * 2 DUC 1 I
+ * 3 DUC 1 Q
+ *
+ * The default value is 0x10
+ *
+ */
+ volatile uint32_t tx_mux;
+
} dsp_tx_regs_t;
#define dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE)
@@ -402,6 +437,29 @@ typedef struct {
volatile uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode, using lower 14 bits
volatile uint32_t adc_mux; // 4 bits -- lowest 2 for adc_i, next for adc_q
+ /*!
+ * \brief input mux configuration.
+ *
+ * This determines which ADC (or constant zero) is connected to
+ * each DDC input. There are N DDCs (1 now). Each has two inputs.
+ *
+ *
+ * Mux value:
+ *
+ * 3 2 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------+-------+-------+-------+-------+-------+-------+-------+
+ * | |Q1 |I1 |Q0 |I0 |
+ * +-------+-------+-------+-------+-------+-------+-------+-------+
+ *
+ * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+ * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+ *
+ * The default value is 0x44444444
+ *
+ */
+ volatile uint32_t rx_mux;
+
} dsp_rx_regs_t;
#define dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE)
diff --git a/usrp2/firmware/lib/u2_init.c b/usrp2/firmware/lib/u2_init.c
index b13396343..948055694 100644
--- a/usrp2/firmware/lib/u2_init.c
+++ b/usrp2/firmware/lib/u2_init.c
@@ -86,6 +86,10 @@ u2_init(void)
ad9777_write_reg(11, 0); // Q dac offset
ad9777_write_reg(12, 0);
+ // Initial values for tx and rx mux registers
+ dsp_tx_regs->tx_mux = 0x10;
+ dsp_rx_regs->rx_mux = 0x44444444;
+
// Set up serdes
output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN);
--
cgit