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changes the behavior slightly so new values were necessary. By explicitly setting alpha and beta to the previous values still worked, though.
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inside the block. This forces a slower decision making routine but allows differential encoding. Gray coding is done using pre_diff_code.
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control loop class and cleaned up the interface.
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gri_control_loop class to handle the inner loop. Had to add it to digital_swig.i to properly wrap the parent functions into Python.
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care of the internal loop. The error and what to do with the phase and freq are left to this block. It also changes the interface so that the PLL's gains are determined by the loop bandwidth.
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the standard loop advance function. This should be used as a parent class of any block that uses a 2nd order control loop (like the PLL, clock recovery, etc blocks).
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normal bpsk is non-differential by default, but can be set to use differential with the right flag.
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factor instead of setting alpha and beta independently. Also cleaning up Costas loop a bit more.
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gain names/settings. Also added concept of gray coding to generic mod/demod and reworked bpsk/qpsk modulators so both work.
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changed the error value limit since we were hitting it constantly before.
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polyphase filterbank.
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taps, more accesors.
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setting gains independently.
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include phase offset setting.
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and is no longer part of the constructor. All variables are exposed in gets and sets, though, for any purposes.
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frequency and phase estimates.
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make shorter test time.
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new FLL in digital instead of gr.
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offline.
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offline.
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code for it.
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for it.
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executable.
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gr-digital.
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