diff options
Diffstat (limited to 'usrp')
| -rwxr-xr-x | usrp/firmware/src/common/build_eeprom.py | 4 | ||||
| -rwxr-xr-x | usrp/host/apps/burn-db-eeprom | 2 | ||||
| -rw-r--r-- | usrp/host/include/usrp/Makefile.am | 1 | ||||
| -rw-r--r-- | usrp/host/include/usrp/db_bitshark_rx.h | 56 | ||||
| -rw-r--r-- | usrp/host/include/usrp/db_flexrf.h | 40 | ||||
| -rw-r--r-- | usrp/host/include/usrp/db_wbxng.h | 39 | ||||
| -rw-r--r-- | usrp/host/lib/Makefile.am | 3 | ||||
| -rw-r--r-- | usrp/host/lib/db_base.cc | 2 | ||||
| -rw-r--r-- | usrp/host/lib/db_bitshark_rx.cc | 417 | ||||
| -rw-r--r-- | usrp/host/lib/db_boards.cc | 5 | ||||
| -rw-r--r-- | usrp/host/lib/db_flexrf.cc | 98 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng.cc | 166 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng_adf4350.cc | 122 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng_adf4350.h | 14 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng_adf4350_regs.cc | 16 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng_adf4350_regs.h | 11 | ||||
| -rw-r--r-- | usrp/host/lib/usrp_dbid.dat | 5 | ||||
| -rw-r--r-- | usrp/usrp.pc.in | 2 |
18 files changed, 785 insertions, 218 deletions
diff --git a/usrp/firmware/src/common/build_eeprom.py b/usrp/firmware/src/common/build_eeprom.py index d73cbbc4f..00c2e3414 100755 --- a/usrp/firmware/src/common/build_eeprom.py +++ b/usrp/firmware/src/common/build_eeprom.py @@ -182,10 +182,6 @@ if __name__ == '__main__': sys.stderr.write ( "You must specify the install prefix with -p PREFIX\n") sys.exit (1) - if not os.path.isdir(options.prefix): - sys.stderr.write ( - "PREFIX dir (" + options.prefix + "), does not exist\n") - sys.exit (1) ihx_filename = args[0] diff --git a/usrp/host/apps/burn-db-eeprom b/usrp/host/apps/burn-db-eeprom index 7ff1e9736..0c908e3d5 100755 --- a/usrp/host/apps/burn-db-eeprom +++ b/usrp/host/apps/burn-db-eeprom @@ -65,12 +65,14 @@ daughterboards = { 'rfx900_mimo_b' : ((FLEX_900_TX_MIMO_B, 0x0000), (FLEX_900_RX_MIMO_B, 0x0000)), 'rfx1200_mimo_b' : ((FLEX_1200_TX_MIMO_B, 0x0000), (FLEX_1200_RX_MIMO_B, 0x0000)), 'rfx1800_mimo_b' : ((FLEX_1800_TX_MIMO_B, 0x0000), (FLEX_1800_RX_MIMO_B, 0x0000)), + 'rfx2200_mimo_b' : ((FLEX_2200_TX_MIMO_B, 0x0000), (FLEX_2200_RX_MIMO_B, 0x0000)), 'rfx2400_mimo_b' : ((FLEX_2400_TX_MIMO_B, 0x0000), (FLEX_2400_RX_MIMO_B, 0x0000)), 'lftx' : ((LF_TX, 0x0000), None), 'lfrx' : (None, (LF_RX, 0x0000)), 'wbx_lo' : ((WBX_LO_TX, 0x0000), (WBX_LO_RX, 0x0000)), 'wbx_ng' : ((WBX_NG_TX, 0x0000), (WBX_NG_RX, 0x0000)), 'xcvr2450' : ((XCVR2450_TX, 0x0000), (XCVR2450_RX, 0x0000)), + 'bitshark_rx' : (None, (BITSHARK_RX, 0x0000)), 'experimental_tx' : ((EXPERIMENTAL_TX, 0x0000), None), 'experimental_rx' : (None, (EXPERIMENTAL_RX, 0x0000)), } diff --git a/usrp/host/include/usrp/Makefile.am b/usrp/host/include/usrp/Makefile.am index cfce51443..2aaf66a53 100644 --- a/usrp/host/include/usrp/Makefile.am +++ b/usrp/host/include/usrp/Makefile.am @@ -26,6 +26,7 @@ usrpincludedir = $(includedir)/usrp usrpinclude_HEADERS = \ db_base.h \ db_basic.h \ + db_bitshark_rx.h \ db_dbs_rx.h \ db_dtt754.h \ db_dtt768.h \ diff --git a/usrp/host/include/usrp/db_bitshark_rx.h b/usrp/host/include/usrp/db_bitshark_rx.h new file mode 100644 index 000000000..f81877d28 --- /dev/null +++ b/usrp/host/include/usrp/db_bitshark_rx.h @@ -0,0 +1,56 @@ +/* -*- c++ -*- */ +// +// Copyright 2010 Free Software Foundation, Inc. +// +// This file is part of GNU Radio +// +// GNU Radio is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either asversion 3, or (at your option) +// any later version. +// +// GNU Radio is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with GNU Radio; see the file COPYING. If not, write to +// the Free Software Foundation, Inc., 51 Franklin Street, +// Boston, MA 02110-1301, USA. + +#ifndef DB_BITSHARK_RX_H +#define DB_BITSHARK_RX_H + +#include <usrp/db_base.h> +#include <vector> +#include <stdint.h> + +class db_bitshark_rx : public db_base +{ +private: + int d_i2c_addr; + // Internal function for interfacing to the card + void _set_pga(int pga_gain); + +protected: + void shutdown(); + +public: + db_bitshark_rx(usrp_basic_sptr usrp, int which); + ~db_bitshark_rx(); + + float gain_min(); + float gain_max(); + float gain_db_per_step(); + double freq_min(); + double freq_max(); + struct freq_result_t set_freq(double freq); + bool set_gain(float gain); + bool set_bw(float bw); + bool set_clock_scheme(uint8_t clock_scheme, uint32_t ref_clock_freq); + bool is_quadrature(); + bool i_and_q_swapped(); +}; + +#endif diff --git a/usrp/host/include/usrp/db_flexrf.h b/usrp/host/include/usrp/db_flexrf.h index 0c834402d..70a55514e 100644 --- a/usrp/host/include/usrp/db_flexrf.h +++ b/usrp/host/include/usrp/db_flexrf.h @@ -138,6 +138,18 @@ protected: //---------------------------------------------------------------------- +class _2200_common : public _AD4360_common +{ + public: + _2200_common(); + ~_2200_common() {} + + double freq_min(); + double freq_max(); +}; + +//---------------------------------------------------------------------- + class _2400_common : public _AD4360_common { public: @@ -212,6 +224,34 @@ public: //------------------------------------------------------------ +class db_flexrf_2200_tx : public flexrf_base_tx +{ + public: + db_flexrf_2200_tx(usrp_basic_sptr usrp, int which); + ~db_flexrf_2200_tx(); + + // Wrapper calls to d_common functions + bool _compute_regs(double freq, int &retR, int &retcontrol, + int &retN, double &retfreq); +}; + +class db_flexrf_2200_rx : public flexrf_base_rx +{ +public: + db_flexrf_2200_rx(usrp_basic_sptr usrp, int which); + ~db_flexrf_2200_rx(); + + float gain_min(); + float gain_max(); + float gain_db_per_step(); + bool i_and_q_swapped(); + + bool _compute_regs(double freq, int &retR, int &retcontrol, + int &retN, double &retfreq); +}; + +//------------------------------------------------------------ + class db_flexrf_2400_tx : public flexrf_base_tx { public: diff --git a/usrp/host/include/usrp/db_wbxng.h b/usrp/host/include/usrp/db_wbxng.h index 8611d4787..9a7829278 100644 --- a/usrp/host/include/usrp/db_wbxng.h +++ b/usrp/host/include/usrp/db_wbxng.h @@ -30,7 +30,7 @@ class adf4350; class wbxng_base : public db_base { public: - wbxng_base(usrp_basic_sptr usrp, int which, int _power_on=0); + wbxng_base(usrp_basic_sptr usrp, int which); ~wbxng_base(); struct freq_result_t set_freq(double freq); @@ -40,31 +40,30 @@ public: double freq_max(); protected: - bool _lock_detect(); + void _write_spi(std::string data); + int _refclk_divisor(); + bool _get_locked(); bool _set_pga(float pga_gain); - int power_on() { return d_power_on; } - int power_off() { return 0; } - bool d_first; int d_spi_format; int d_spi_enable; int d_power_on; int d_PD; - adf4350 *d_common; + boost::shared_ptr<adf4350> d_common; }; // ---------------------------------------------------------------- -class wbxng_base_tx : public wbxng_base +class db_wbxng_tx : public wbxng_base { protected: void shutdown(); public: - wbxng_base_tx(usrp_basic_sptr usrp, int which, int _power_on=0); - ~wbxng_base_tx(); + db_wbxng_tx(usrp_basic_sptr usrp, int which); + ~db_wbxng_tx(); float gain_min(); float gain_max(); @@ -75,36 +74,20 @@ public: bool set_gain(float gain); }; -class wbxng_base_rx : public wbxng_base +class db_wbxng_rx : public wbxng_base { protected: void shutdown(); bool _set_attn(float attn); public: - wbxng_base_rx(usrp_basic_sptr usrp, int which, int _power_on=0); - ~wbxng_base_rx(); + db_wbxng_rx(usrp_basic_sptr usrp, int which); + ~db_wbxng_rx(); bool set_auto_tr(bool on); bool select_rx_antenna(int which_antenna); bool select_rx_antenna(const std::string &which_antenna); bool set_gain(float gain); -}; - -// ---------------------------------------------------------------- - -class db_wbxng_tx : public wbxng_base_tx -{ - public: - db_wbxng_tx(usrp_basic_sptr usrp, int which); - ~db_wbxng_tx(); -}; - -class db_wbxng_rx : public wbxng_base_rx -{ -public: - db_wbxng_rx(usrp_basic_sptr usrp, int which); - ~db_wbxng_rx(); float gain_min(); float gain_max(); diff --git a/usrp/host/lib/Makefile.am b/usrp/host/lib/Makefile.am index 5848412c9..23889fc85 100644 --- a/usrp/host/lib/Makefile.am +++ b/usrp/host/lib/Makefile.am @@ -24,7 +24,7 @@ common_INCLUDES = $(USRP_INCLUDES) $(USB_INCLUDES) lib_LTLIBRARIES = libusrp.la -libusrp_la_common_LDFLAGS = $(NO_UNDEFINED) -version-info 0:0:0 $(BOOST_LDFLAGS) +libusrp_la_common_LDFLAGS = $(NO_UNDEFINED) $(LTVERSIONFLAGS) $(BOOST_LDFLAGS) libusrp_la_common_LIBADD = \ $(USB_LIBS) \ @@ -120,6 +120,7 @@ libusrp_la_common_SOURCES = \ db_boards.cc \ db_base.cc \ db_basic.cc \ + db_bitshark_rx.cc \ db_tv_rx.cc \ db_tv_rx_mimo.cc \ db_flexrf.cc \ diff --git a/usrp/host/lib/db_base.cc b/usrp/host/lib/db_base.cc index 1cb463429..b4fb45c51 100644 --- a/usrp/host/lib/db_base.cc +++ b/usrp/host/lib/db_base.cc @@ -238,7 +238,7 @@ int db_base::_refclk_divisor() { // Return value to stick in REFCLK_DIVISOR register - throw std::runtime_error("_reflck_divisor() called from base class\n");; + throw std::runtime_error("_refclk_divisor() called from base class\n");; } bool diff --git a/usrp/host/lib/db_bitshark_rx.cc b/usrp/host/lib/db_bitshark_rx.cc new file mode 100644 index 000000000..5368866d8 --- /dev/null +++ b/usrp/host/lib/db_bitshark_rx.cc @@ -0,0 +1,417 @@ +// +// Copyright 2010 Free Software Foundation, Inc. +// +// This file is part of GNU Radio +// +// GNU Radio is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either asversion 3, or (at your option) +// any later version. +// +// GNU Radio is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with GNU Radio; see the file COPYING. If not, write to +// the Free Software Foundation, Inc., 51 Franklin Street, +// Boston, MA 02110-1301, USA. + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <usrp/db_bitshark_rx.h> +#include <db_base_impl.h> +#include <cmath> +#include <cstdio> +#include <string.h> +#include <stdint.h> + +/* Note: Thie general structure of this file is based on the db_dbsrx.cc + codebase for the dbsrx daughterboard. */ + +/* The following defines specify the address map provided by the + Bitshark card. These registers are all accessed over I2C. */ +#define RF_CENTER_FREQ_REG 0x00 +#define RF_CHAN_FILTER_BW_REG 0x01 +#define RF_GAIN_REG 0x02 +#define BB_GAIN_REG 0x03 +#define ADF4350_REG 0x10 +#define SKY73202_REG 0x11 +#define CLOCK_SCHEME_REG 0x20 + +/* The following table lists the registers provided by the BURX board that + are accessible over I2C: + -------------------------------------------------------- + |RegAddr: 0x00-RF Center Freq register | + |4-bytes 0x00| + |4-byte unsigned RF center freq (in KHz)| + |RegAddr: 0x01-RF channel filter bandwidth register | + |4-bytes 0x00| + |4-byte unsigned RF channel filter bw (in KHz)| + |RegAddr: 0x02-RF gain register | + |7-bytes 0x00| + |1-byte signed RF gain (in dB)| + |RegAddr: 0x03-Baseband gain register | + |4-bytes 0x00| + |4-byte signed baseband filter gain (in dB)| + |RegAddr: 0x10-ADF4350 register | + |4-bytes 0x00| + |4-byte ADF4350 register value (actual ADF4350 reg addr embedded + within 4-byte value)| + |RegAddr: 0x11-SKY73202 register | + |5-bytes 0x00| + |1-byte reg 0 of SKY73202 | + |1-byte reg 1 of SKY73202 | + |1-byte reg 2 of SKY73202 | + |RegAddr: 0x20-Clock Scheme | + |3-bytes 0x00| + |1-byte indicating clocking scheme: + -0x00 -> BURX local TCXO off, BURX accepts ref clock from + USRP (freq of USRP's ref clock specified in bytes 2-5) + -0x01 -> BURX local TCXO on, BURX uses its local TCXO as its ref + clock, TCXO signal output for use by USRP | + |4-byte USRP ref clock freq in hz (only needed if byte 1 set to 0x00) | + + --------------------------------------------------------------------------- + + As an example, lets say the client wants to set an RF center freq of + 1000 MHz. In KHz, this translates to 1000000 (resolution is only down to + steps of 1 KHz), which is 0x000F4240 in hex. So the complete 9-byte I2C + sequence that the client should send is as follows: + byte 0: 0x00-register 0x00 is the target of the write operation + bytes 1-4: 0x00 (padding) + byte 5: 0x40 (LSB of the 1000000 KHz value, in hex) + byte 6: 0x42 + byte 7: 0x0F + byte 8: 0x00 (MSB of the 1000000 KHz value, in hex) + + If using the usrper cmd-line application on a PC, this sequence would + be sent as follows (assuming that the BURX is in slot A): + + # usrper i2c_write 0x47 000000000040420F00 + + How about another example...lets say the client wants to setup the clock + scheme to use scheme #1 where the 26 MHz TCXO on the BURX board is enabled, + and is provided to the USRP. 26 MHz (i.e. 26 million), in hex, is 0x18CBA80. + So the complete 9-byte I2C sequence that the client should send is as follows: + byte 0: 0x20-register 0x20 is the target of the write operation + bytes 1-3: 0x00 (padding) + byte 4: 0x01 (indicating that clock scheme #1 is wanted) + byte 5: 0x80 (LSB of the BURX ref clk freq) + byte 6: 0xBA + byte 7: 0x8C + byte 8: 0x01 (MSB of the BURX ref clk freq) + + To enable the BURX local ref clk, which will also make it available on the + on-board U.FL connector as a source for the USRP, a user can also use + the usrper cmd-line application on a PC. The following sequence would + be sent (assuming that the BURX is in slot A): + + # usrper i2c_write 0x47 200000000180BA8C01 + +*/ + +#define NUM_BYTES_IN_I2C_CMD 9 + +/*****************************************************************************/ + +db_bitshark_rx::db_bitshark_rx(usrp_basic_sptr _usrp, int which) + : db_base(_usrp, which) +{ + // Control Bitshark receiver USRP daughterboard. + // + // @param usrp: instance of usrp.source_c + // @param which: which side: 0, 1 corresponding to RX_A or RX_B respectively + + // turn off all outputs + usrp()->_write_oe(d_which, 0, 0xffff); + + if (which == 0) + { + d_i2c_addr = 0x47; + } + else + { + d_i2c_addr = 0x45; + } + + // initialize gain + set_gain((gain_min() + gain_max()) / 2.0); + + // by default, assume we're using the USRPs clock as the ref clk, + // so setup the clock scheme and frequency. If the user wants + // to use the Bitshark's TCXO, the clock scheme should be set + // to 1, the freq should be set to 26000000, and a top-level + // 'make' and 'make install' needs to be executed. In addition, + // a U.FL to SMA cable needs to connect J6 on the Bitshark to + // the external clk input on the USRP + set_clock_scheme(0,64000000); + + set_bw(8e6); // Default IF bandwidth to match USRP1 max host bandwidth + + bypass_adc_buffers(true); +} + +db_bitshark_rx::~db_bitshark_rx() +{ + shutdown(); +} + +/************ Private Functions **********************/ + +void +db_bitshark_rx::_set_pga(int pga_gain) +{ + assert(pga_gain>=0 && pga_gain<=20); + if(d_which == 0) + { + usrp()->set_pga (0, pga_gain); + usrp()->set_pga (1, pga_gain); + } + else + { + usrp()->set_pga (2, pga_gain); + usrp()->set_pga (3, pga_gain); + } +} + +/************ Public Functions **********************/ +void +db_bitshark_rx::shutdown() +{ + if (!d_is_shutdown) + { + d_is_shutdown = true; + } +} + +bool +db_bitshark_rx::set_bw (float bw) +{ + std::vector<int> args(NUM_BYTES_IN_I2C_CMD,0); + uint16_t rf_bw_in_khz = (uint16_t)(bw/1000.0); + char val[4]; + bool result = false; + uint8_t try_count = 0; + + memset(val,0x00,4); + if (rf_bw_in_khz < 660 || rf_bw_in_khz > 56000) + { + fprintf(stderr, "db_bitshark_rx::set_bw: bw (=%d) must be between 660 KHz and 56 MHz inclusive\n", rf_bw_in_khz); + return false; + } + //fprintf(stdout,"Setting bw: requested bw in khz is %d\r\n",rf_bw_in_khz); + memcpy(val,&rf_bw_in_khz,4); + args[0] = RF_CHAN_FILTER_BW_REG; + args[5] = val[0]; + args[6] = val[1]; + args[7] = val[2]; + args[8] = val[3]; + while ((result != true) && (try_count < 3)) + { + result=usrp()->write_i2c (d_i2c_addr, int_seq_to_str (args)); + try_count++; + } + + if (result == false) + { + fprintf(stderr, "db_bitshark_rx:set_bw: giving up after 3 tries without success\n"); + } + + return result; +} + +/* The gain referenced below is RF gain only. There are two independent + gain settings at RF: a digital step attenuator (providing 0, -6, -12, and + -18 dB of attenuation), and a second LNA (LNA2) that provides ~25 dB of + gain (roughly...it actually depends on the RF freq). So combining these + two stages can provide an overall gain range from 0 (which is mapped + to -18 dB on the step attenuator + LNA2 turned off) to 42 (which is + mapped to 0 dB on the step attenuator + LNA2 turned on). + + There could be better ways to map these, but this is sufficient for + now. */ +float +db_bitshark_rx::gain_min() +{ + return 0; +} + +float +db_bitshark_rx::gain_max() +{ + return 42; +} + +float +db_bitshark_rx::gain_db_per_step() +{ + return 6; +} + +bool +db_bitshark_rx::set_gain(float gain) +{ + // Set the gain. + // + // @param gain: RF gain in decibels, range of 0-42 + // @returns True/False + + std::vector<int> args(NUM_BYTES_IN_I2C_CMD,0); + bool result = false; + uint8_t try_count = 0; + + if (gain < gain_min() || gain > gain_max()) + { + fprintf(stderr,"db_bitshark_rx::set_gain: gain (=%f) must be between %f and %f inclusive\n", gain,gain_min(),gain_max()); + return false; + } + //fprintf(stdout,"db_bitshark_rx::set_gain: requested gain of %f\r\n",gain); + args[0] = RF_GAIN_REG; + args[5] = (int)gain; + + while ((result != true) && (try_count < 3)) + { + result=usrp()->write_i2c (d_i2c_addr, int_seq_to_str (args)); + try_count++; + } + + if (result == false) + { + fprintf(stderr, "db_bitshark_rx:set_gain: giving up after 3 tries without success\n"); + } + + return result; +} + + +bool +db_bitshark_rx::set_clock_scheme(uint8_t clock_scheme, uint32_t ref_clk_freq) +{ + // Set the clock scheme for determining how the BURX + // dboard receives its clock. Note: Ideally, the constructor for the + // BURX board could simply call this method to set how it wants the + // clock scheme configured. However, depending on the application + // using the daughterboard, the constructor may run _after_ some + // other portion of the application needs the FPGA. And if the + // the clock source for the FPGA was the BURX's 26 MHz TCXO, we're in + // a chicken-before-the-egg dilemna. So the solution is to leave + // this function here for reference in case an app wants to use it, + // and also give the user the ability to set the clock scheme through + // the usrper cmd-line application (see example at the top of this + // file). + // + // @param clock_scheme + // @param ref_clk_freq in Hz + // @returns True/False + + std::vector<int> args(NUM_BYTES_IN_I2C_CMD,0); + bool result = false; + uint8_t try_count = 0; + char val[4]; + + if (clock_scheme > 1) + { + fprintf(stderr,"db_bitshark_rx::set_clock_scheme: invalid scheme %d\n",clock_scheme); + return false; + } + //fprintf(stdout,"db_bitshark_rx::set_clock_scheme: requested clock schem of %d with freq %d Hz \n",clock_scheme,ref_clk_freq); + memcpy(val,&ref_clk_freq,4); + args[0] = CLOCK_SCHEME_REG; + args[4] = (int)clock_scheme; + args[5] = val[0]; + args[6] = val[1]; + args[7] = val[2]; + args[8] = val[3]; + + while ((result != true) && (try_count < 3)) + { + result=usrp()->write_i2c (d_i2c_addr, int_seq_to_str (args)); + try_count++; + } + + if (result == false) + { + fprintf(stderr, "db_bitshark_rx:set_clock_scheme: giving up after 3 tries without success\n"); + } + return result; +} + +double +db_bitshark_rx::freq_min() +{ + return 300e6; +} + +double +db_bitshark_rx::freq_max() +{ + return 4e9; +} + +struct freq_result_t +db_bitshark_rx::set_freq(double freq) +{ + // Set the frequency. + // + // @param freq: target RF frequency in Hz + // @type freq: double + // + // @returns (ok, actual_baseband_freq) where: + // ok is True or False and indicates success or failure, + // actual_baseband_freq is RF frequency that corresponds to DC in the IF. + + std::vector<int> args(NUM_BYTES_IN_I2C_CMD,0); + std::vector<int> bytes(2); + char val[4]; + freq_result_t act_freq = {false, 0}; + uint32_t freq_in_khz = (uint32_t)(freq/1000.0); + bool result = false; + uint8_t try_count = 0; + + memset(val,0x00,4); + if(!(freq>=freq_min() && freq<=freq_max())) + { + return act_freq; + } + + //fprintf(stdout,"db_bitshark_rx::set_freq: requested freq is %d KHz\n",freq_in_khz); + memcpy(val,&freq_in_khz,4); + args[0] = RF_CENTER_FREQ_REG; + args[5] = val[0]; + args[6] = val[1]; + args[7] = val[2]; + args[8] = val[3]; + + while ((result != true) && (try_count < 3)) + { + result=usrp()->write_i2c (d_i2c_addr, int_seq_to_str (args)); + try_count++; + } + + if (result == false) + { + fprintf(stderr, "db_bitshark_rx:set_freq: giving up after 3 tries without success\n"); + } + + act_freq.ok = result; + act_freq.baseband_freq = (double)freq; + return act_freq; +} + +bool +db_bitshark_rx::is_quadrature() +{ + // Return True if this board requires both I & Q analog channels. + return true; +} + +bool +db_bitshark_rx::i_and_q_swapped() +{ + // Returns True since our I and Q channels are swapped + return true; +} diff --git a/usrp/host/lib/db_boards.cc b/usrp/host/lib/db_boards.cc index 590d8132d..9324d58ee 100644 --- a/usrp/host/lib/db_boards.cc +++ b/usrp/host/lib/db_boards.cc @@ -36,6 +36,7 @@ #include <usrp/db_xcvr2450.h> #include <usrp/db_dtt754.h> #include <usrp/db_dtt768.h> +#include <usrp/db_bitshark_rx.h> #include <cstdio> std::vector<db_base_sptr> @@ -209,6 +210,10 @@ instantiate_dbs(int dbid, usrp_basic_sptr usrp, int which_side) db.push_back(db_base_sptr(new db_dtt768(usrp, which_side))); break; + case(USRP_DBID_BITSHARK_RX): + db.push_back(db_base_sptr(new db_bitshark_rx(usrp, which_side))); + break; + case(-1): if (boost::dynamic_pointer_cast<usrp_basic_tx>(usrp)){ db.push_back(db_base_sptr(new db_basic_tx(usrp, which_side))); diff --git a/usrp/host/lib/db_flexrf.cc b/usrp/host/lib/db_flexrf.cc index 07ac2be3b..2819c19bd 100644 --- a/usrp/host/lib/db_flexrf.cc +++ b/usrp/host/lib/db_flexrf.cc @@ -639,6 +639,38 @@ _AD4360_common::_prescaler() //---------------------------------------------------------------------- +_2200_common::_2200_common() + : _AD4360_common() +{ + // Band-specific R-Register Values + d_R_DIV = 16; // bits 15:2 + + // Band-specific C-Register values + d_P = 1; // bits 23,22 Div by 16/17 + d_CP2 = 7; // bits 19:17 + d_CP1 = 7; // bits 16:14 + + // Band specifc N-Register Values + d_DIVSEL = 0; // bit 23 + d_DIV2 = 0; // bit 22 + d_CPGAIN = 0; // bit 21 + d_freq_mult = 1; +} + +double +_2200_common::freq_min() +{ + return 2000e6; +} + +double +_2200_common::freq_max() +{ + return 2400e6; +} + +//---------------------------------------------------------------------- + _2400_common::_2400_common() : _AD4360_common() { @@ -811,6 +843,72 @@ _400_rx::_400_rx() //------------------------------------------------------------ +db_flexrf_2200_tx::db_flexrf_2200_tx(usrp_basic_sptr usrp, int which) + : flexrf_base_tx(usrp, which) +{ + d_common = new _2200_common(); +} + +db_flexrf_2200_tx::~db_flexrf_2200_tx() +{ +} + +bool +db_flexrf_2200_tx::_compute_regs(double freq, int &retR, int &retcontrol, + int &retN, double &retfreq) +{ + return d_common->_compute_regs(_refclk_freq(), freq, retR, + retcontrol, retN, retfreq); +} + + + +db_flexrf_2200_rx::db_flexrf_2200_rx(usrp_basic_sptr usrp, int which) + : flexrf_base_rx(usrp, which) +{ + d_common = new _2200_common(); + set_gain((gain_min() + gain_max()) / 2.0); // initialize gain +} + +db_flexrf_2200_rx::~db_flexrf_2200_rx() +{ +} + +float +db_flexrf_2200_rx::gain_min() +{ + return usrp()->pga_min(); +} + +float +db_flexrf_2200_rx::gain_max() +{ + return usrp()->pga_max()+70; +} + +float +db_flexrf_2200_rx::gain_db_per_step() +{ + return 0.05; +} + + +bool +db_flexrf_2200_rx::i_and_q_swapped() +{ + return true; +} + +bool +db_flexrf_2200_rx::_compute_regs(double freq, int &retR, int &retcontrol, + int &retN, double &retfreq) +{ + return d_common->_compute_regs(_refclk_freq(), freq, retR, + retcontrol, retN, retfreq); +} + +//------------------------------------------------------------ + db_flexrf_2400_tx::db_flexrf_2400_tx(usrp_basic_sptr usrp, int which) : flexrf_base_tx(usrp, which) { diff --git a/usrp/host/lib/db_wbxng.cc b/usrp/host/lib/db_wbxng.cc index bd836dfe3..89200653e 100644 --- a/usrp/host/lib/db_wbxng.cc +++ b/usrp/host/lib/db_wbxng.cc @@ -46,8 +46,8 @@ #define ATTN_SHIFT 8 #define ATTN_MASK (63 << ATTN_SHIFT) -wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which, int _power_on) - : db_base(_usrp, which), d_power_on(_power_on) +wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which) + : db_base(_usrp, which) { /* @param usrp: instance of usrp.source_c @@ -67,8 +67,12 @@ wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which, int _power_on) wbxng_base::~wbxng_base() { - if (d_common) - delete d_common; +} + +int +wbxng_base::_refclk_divisor() +{ + return 1; } struct freq_result_t @@ -83,8 +87,19 @@ wbxng_base::set_freq(double freq) // clamp freq freq_t int_freq = freq_t(std::max(freq_min(), std::min(freq, freq_max()))); - bool ok = d_common->_set_freq(int_freq*2); - double freq_result = (double) d_common->_get_freq()/2.0; + bool ok = d_common->_set_freq(int_freq*2, _refclk_freq()); + + _write_spi(d_common->compute_register(5)); + _write_spi(d_common->compute_register(4)); + _write_spi(d_common->compute_register(3)); + /* load involved registers */ + _write_spi(d_common->compute_register(2)); + _write_spi(d_common->compute_register(1)); + _write_spi(d_common->compute_register(0)); + + double freq_result = (double) d_common->_get_freq(_refclk_freq())/2.0; + + //ok &= _get_locked(); struct freq_result_t args = {ok, freq_result}; /* Wait before reading Lock Detect*/ @@ -144,10 +159,22 @@ wbxng_base::freq_max() return (double) d_common->_get_max_freq()/2.0; } +bool +wbxng_base::_get_locked(void) +{ + return usrp()->read_io(d_which) & PLL_LOCK_DETECT; +} + +void +wbxng_base::_write_spi(std::string data) +{ + usrp()->_write_spi(0, d_spi_enable, d_spi_format, data); +} + // ---------------------------------------------------------------- -wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on) - : wbxng_base(_usrp, which, _power_on) +db_wbxng_tx::db_wbxng_tx(usrp_basic_sptr _usrp, int which) + : wbxng_base(_usrp, which) { /* @param usrp: instance of usrp.sink_c @@ -161,40 +188,48 @@ wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on) d_spi_enable = SPI_ENABLE_TX_B; } - d_common = new adf4350(_usrp, d_which, d_spi_enable); + d_common = boost::shared_ptr<adf4350> (new adf4350()); + + /* Initialize the registers. */ + _write_spi(d_common->compute_register(5)); + _write_spi(d_common->compute_register(4)); + _write_spi(d_common->compute_register(3)); + _write_spi(d_common->compute_register(2)); + _write_spi(d_common->compute_register(1)); + _write_spi(d_common->compute_register(0)); // power up the transmit side, but don't enable the mixer - usrp()->_write_oe(d_which,(RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5)); - usrp()->write_io(d_which, (power_on()|RX_TXN|ENABLE_33|ENABLE_5), (RX_TXN|ENABLE_33|ENABLE_5)); + usrp()->_write_oe(d_which,(PLL_CE|PLL_PDBRF|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5)); + usrp()->write_io(d_which, (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX_TXN|ENABLE_33|ENABLE_5)); //set_lo_offset(4e6); // Disable VCO/PLL - d_common->_enable(true); + //d_common->_enable(true); + usrp()->write_io(d_which, (PLL_PDBRF), (PLL_PDBRF)); - set_gain((gain_min() + gain_max()) / 2.0); // initialize gain + set_gain(gain_min()); // initialize gain } -wbxng_base_tx::~wbxng_base_tx() +db_wbxng_tx::~db_wbxng_tx() { shutdown(); } - void -wbxng_base_tx::shutdown() +db_wbxng_tx::shutdown() { - // fprintf(stderr, "wbxng_base_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown); + // fprintf(stderr, "db_wbxng_tx::shutdown d_is_shutdown = %d\n", d_is_shutdown); if (!d_is_shutdown){ d_is_shutdown = true; // do whatever there is to do to shutdown // Disable VCO/PLL - d_common->_enable(false); + //d_common->_enable(false); + usrp()->write_io(d_which, 0, (PLL_PDBRF)); // Power down and leave the T/R switch in the R position - usrp()->write_io(d_which, (power_off()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5)); - + usrp()->write_io(d_which, (RX_TXN), (PLL_CE|PLL_PDBRF|RX_TXN|ENABLE_33|ENABLE_5)); /* _write_control(_compute_control_reg()); @@ -205,7 +240,7 @@ wbxng_base_tx::shutdown() } bool -wbxng_base_tx::set_auto_tr(bool on) +db_wbxng_tx::set_auto_tr(bool on) { bool ok = true; if(on) { @@ -222,7 +257,7 @@ wbxng_base_tx::set_auto_tr(bool on) } bool -wbxng_base_tx::set_enable(bool on) +db_wbxng_tx::set_enable(bool on) { /* Enable transmitter if on is true @@ -244,25 +279,25 @@ wbxng_base_tx::set_enable(bool on) } float -wbxng_base_tx::gain_min() +db_wbxng_tx::gain_min() { return 0.0; } float -wbxng_base_tx::gain_max() +db_wbxng_tx::gain_max() { return 25.0; } float -wbxng_base_tx::gain_db_per_step() +db_wbxng_tx::gain_db_per_step() { return gain_max()/(1+(1.4-0.5)*4096/3.3); } bool -wbxng_base_tx::set_gain(float gain) +db_wbxng_tx::set_gain(float gain) { /* Set the gain. @@ -299,8 +334,8 @@ wbxng_base_tx::set_gain(float gain) /**************************************************************************/ -wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on) - : wbxng_base(_usrp, which, _power_on) +db_wbxng_rx::db_wbxng_rx(usrp_basic_sptr _usrp, int which) + : wbxng_base(_usrp, which) { /* @param usrp: instance of usrp.source_c @@ -314,15 +349,24 @@ wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on) d_spi_enable = SPI_ENABLE_RX_B; } - d_common = new adf4350(_usrp, d_which, d_spi_enable); - - // Disable VCO/PLL - d_common->_enable(true); + d_common = boost::shared_ptr<adf4350> (new adf4350()); - usrp()->_write_oe(d_which, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5)); - usrp()->write_io(d_which, (power_on()|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5)); + /* Initialize the registers. */ + _write_spi(d_common->compute_register(5)); + _write_spi(d_common->compute_register(4)); + _write_spi(d_common->compute_register(3)); + _write_spi(d_common->compute_register(2)); + _write_spi(d_common->compute_register(1)); + _write_spi(d_common->compute_register(0)); + + usrp()->_write_oe(d_which, (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5)); + usrp()->write_io(d_which, (PLL_CE|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5)); //fprintf(stderr,"Setting WBXNG RXBB on"); + // Enable VCO/PLL + //d_common->_enable(true); + usrp()->write_io(d_which, (PLL_PDBRF), (PLL_PDBRF)); + // set up for RX on TX/RX port select_rx_antenna("TX/RX"); @@ -331,43 +375,46 @@ wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on) /* set_lo_offset(-4e6); */ + + set_gain(gain_min()); // initialize gain } -wbxng_base_rx::~wbxng_base_rx() +db_wbxng_rx::~db_wbxng_rx() { shutdown(); } void -wbxng_base_rx::shutdown() +db_wbxng_rx::shutdown() { - // fprintf(stderr, "wbxng_base_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown); + // fprintf(stderr, "db_wbxng_rx::shutdown d_is_shutdown = %d\n", d_is_shutdown); if (!d_is_shutdown){ d_is_shutdown = true; // do whatever there is to do to shutdown // Power down VCO/PLL - d_common->_enable(false); + //d_common->_enable(false); + usrp()->write_io(d_which, 0, (PLL_PDBRF)); - // fprintf(stderr, "wbxng_base_rx::shutdown before _write_control\n"); + // fprintf(stderr, "db_wbxng_rx::shutdown before _write_control\n"); //_write_control(_compute_control_reg()); - // fprintf(stderr, "wbxng_base_rx::shutdown before _enable_refclk\n"); + // fprintf(stderr, "db_wbxng_rx::shutdown before _enable_refclk\n"); _enable_refclk(false); // turn off refclk - // fprintf(stderr, "wbxng_base_rx::shutdown before set_auto_tr\n"); + // fprintf(stderr, "db_wbxng_rx::shutdown before set_auto_tr\n"); set_auto_tr(false); // Power down - usrp()->write_io(d_which, power_off(), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5)); + usrp()->write_io(d_which, 0, (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5)); - // fprintf(stderr, "wbxng_base_rx::shutdown after set_auto_tr\n"); + // fprintf(stderr, "db_wbxng_rx::shutdown after set_auto_tr\n"); } } bool -wbxng_base_rx::set_auto_tr(bool on) +db_wbxng_rx::set_auto_tr(bool on) { bool ok = true; if(on) { @@ -384,7 +431,7 @@ wbxng_base_rx::set_auto_tr(bool on) } bool -wbxng_base_rx::select_rx_antenna(int which_antenna) +db_wbxng_rx::select_rx_antenna(int which_antenna) { /* Specify which antenna port to use for reception. @@ -404,7 +451,7 @@ wbxng_base_rx::select_rx_antenna(int which_antenna) } bool -wbxng_base_rx::select_rx_antenna(const std::string &which_antenna) +db_wbxng_rx::select_rx_antenna(const std::string &which_antenna) { /* Specify which antenna port to use for reception. @@ -426,7 +473,7 @@ wbxng_base_rx::select_rx_antenna(const std::string &which_antenna) } bool -wbxng_base_rx::set_gain(float gain) +db_wbxng_rx::set_gain(float gain) { /* Set the gain. @@ -441,7 +488,6 @@ wbxng_base_rx::set_gain(float gain) float pga_gain, agc_gain; float maxgain = gain_max() - usrp()->pga_max(); - float mingain = gain_min(); if(gain > maxgain) { pga_gain = gain-maxgain; assert(pga_gain <= usrp()->pga_max()); @@ -456,7 +502,7 @@ wbxng_base_rx::set_gain(float gain) } bool -wbxng_base_rx::_set_attn(float attn) +db_wbxng_rx::_set_attn(float attn) { int attn_code = int(floor(attn/0.5)); unsigned int iobits = (~attn_code) << ATTN_SHIFT; @@ -464,27 +510,6 @@ wbxng_base_rx::_set_attn(float attn) return usrp()->write_io(d_which, iobits, ATTN_MASK); } -// ---------------------------------------------------------------- - -db_wbxng_tx::db_wbxng_tx(usrp_basic_sptr usrp, int which) - : wbxng_base_tx(usrp, which) -{ -} - -db_wbxng_tx::~db_wbxng_tx() -{ -} - -db_wbxng_rx::db_wbxng_rx(usrp_basic_sptr usrp, int which) - : wbxng_base_rx(usrp, which) -{ - set_gain((gain_min() + gain_max()) / 2.0); // initialize gain -} - -db_wbxng_rx::~db_wbxng_rx() -{ -} - float db_wbxng_rx::gain_min() { @@ -503,7 +528,6 @@ db_wbxng_rx::gain_db_per_step() return 0.05; } - bool db_wbxng_rx::i_and_q_swapped() { diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc index c17e8d670..f1ab63d82 100644 --- a/usrp/host/lib/db_wbxng_adf4350.cc +++ b/usrp/host/lib/db_wbxng_adf4350.cc @@ -27,9 +27,7 @@ #include <stdio.h> #define FREQ_C(freq) uint64_t(freq) -#define INPUT_REF_FREQ FREQ_C(64e6) #define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom)) -#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */ #define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */ #define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */ #define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */ @@ -42,95 +40,46 @@ #define MUX_PIN (1 << 1) #define LD_PIN (1 << 0) -adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable) +adf4350::adf4350() { - /* Initialize the pin directions. */ - - d_usrp = _usrp; - d_which = _which; - d_spi_enable = _spi_enable; - d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0; - - d_regs = new adf4350_regs(this); - - /* Outputs */ - d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN)); - d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN)); - - /* Initialize the pin levels. */ - _enable(true); - /* Initialize the registers. */ - d_regs->_load_register(5); - d_regs->_load_register(4); - d_regs->_load_register(3); - d_regs->_load_register(2); - d_regs->_load_register(1); - d_regs->_load_register(0); + d_regs = new adf4350_regs(); } adf4350::~adf4350() { - d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN)); delete d_regs; } -freq_t -adf4350::_get_max_freq(void) -{ - return MAX_FREQ; -} - -freq_t -adf4350::_get_min_freq(void) -{ - return MIN_FREQ; -} - -bool -adf4350::_get_locked(void) -{ - return d_usrp->read_io(d_which) & LD_PIN; -} - -void -adf4350::_enable(bool enable) +std::string +adf4350::compute_register(uint8_t addr) { - if (enable){ /* chip enable */ - d_usrp->write_io(d_which, (PDB_RF_PIN), (PDB_RF_PIN)); - }else{ - d_usrp->write_io(d_which, 0, (PDB_RF_PIN)); - } -} + uint32_t data = d_regs->compute_register(addr); -void -adf4350::_write(uint8_t addr, uint32_t data) -{ data |= addr; - // create str from data here + // create std::string from data here char s[4]; s[0] = (char)((data >> 24) & 0xff); s[1] = (char)((data >> 16) & 0xff); s[2] = (char)((data >> 8) & 0xff); s[3] = (char)(data & 0xff); - std::string str(s, 4); - - timespec t; - t.tv_sec = 0; - t.tv_nsec = 5e6; + return std::string(s, 4); +} - nanosleep(&t, NULL); - d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str); - nanosleep(&t, NULL); +freq_t +adf4350::_get_max_freq(void) +{ + return MAX_FREQ; +} - //fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data); - /* pulse latch */ - //d_usrp->write_io(d_which, 1, LE_PIN); - //d_usrp->write_io(d_which, 0, LE_PIN); +freq_t +adf4350::_get_min_freq(void) +{ + return MIN_FREQ; } bool -adf4350::_set_freq(freq_t freq) +adf4350::_set_freq(freq_t freq, freq_t refclock_freq) { /* Set the frequency by setting int, frac, mod, r, div */ if (freq > MAX_FREQ || freq < MIN_FREQ) return false; @@ -147,7 +96,7 @@ adf4350::_set_freq(freq_t freq) d_regs->d_divider_select++; //double the divider } /* Ramp up the R divider until the N divider is at least the minimum. */ - //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq; + //d_regs->d_10_bit_r_counter = refclock_freq*MIN_INT_DIV/freq; d_regs->d_10_bit_r_counter = 2; uint64_t n_mod; do{ @@ -155,7 +104,7 @@ adf4350::_set_freq(freq_t freq) n_mod = freq; n_mod *= d_regs->d_10_bit_r_counter; n_mod *= d_regs->d_mod; - n_mod /= INPUT_REF_FREQ; + n_mod /= refclock_freq; /* calculate int and frac */ d_regs->d_int = n_mod/d_regs->d_mod; d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff); @@ -169,38 +118,31 @@ adf4350::_set_freq(freq_t freq) }while(d_regs->d_int < min_int_div); /* calculate the band select so PFD is under 125 KHz */ d_regs->d_8_bit_band_select_clock_divider_value = \ - INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1; + refclock_freq/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1; /* fprintf(stderr, "Band Selection: Div %u, Freq %lu\n", d_regs->d_8_bit_band_select_clock_divider_value, - INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1 + refclock_freq/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1 ); */ - d_regs->_load_register(5); - d_regs->_load_register(3); - d_regs->_load_register(1); - /* load involved registers */ - d_regs->_load_register(2); - d_regs->_load_register(4); - d_regs->_load_register(0); /* register 0 must be last */ return true; } freq_t -adf4350::_get_freq(void) +adf4350::_get_freq(freq_t refclock_freq) { /* Calculate the freq from int, frac, mod, ref, r, div: * freq = (int + frac/mod) * (ref/r) * Keep precision by doing multiplies first: * freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div) */ - uint64_t temp; - temp = d_regs->d_int; - temp *= d_regs->d_mod; - temp += d_regs->d_frac; - temp *= INPUT_REF_FREQ; - temp /= d_regs->d_mod; - temp /= d_regs->d_10_bit_r_counter; - temp /= (1 << d_regs->d_divider_select); - return temp; + uint64_t freq; + freq = d_regs->d_int; + freq *= d_regs->d_mod; + freq += d_regs->d_frac; + freq *= refclock_freq; + freq /= d_regs->d_mod; + freq /= d_regs->d_10_bit_r_counter; + freq /= (1 << d_regs->d_divider_select); + return freq; } diff --git a/usrp/host/lib/db_wbxng_adf4350.h b/usrp/host/lib/db_wbxng_adf4350.h index 2b0783c20..ce8cbf4b1 100644 --- a/usrp/host/lib/db_wbxng_adf4350.h +++ b/usrp/host/lib/db_wbxng_adf4350.h @@ -31,22 +31,16 @@ class adf4350_regs; class adf4350 { public: - adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable); + adf4350(); ~adf4350(); void _update(); - bool _get_locked(); - void _enable(bool enable); - void _write(uint8_t addr, uint32_t data); - bool _set_freq(freq_t freq); - freq_t _get_freq(); + std::string compute_register(uint8_t addr); + bool _set_freq(freq_t freq, freq_t refclock_freq); + freq_t _get_freq(freq_t refclock_freq); freq_t _get_max_freq(); freq_t _get_min_freq(); protected: - usrp_basic_sptr d_usrp; - int d_which; - int d_spi_enable; - int d_spi_format; adf4350_regs *d_regs; }; diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.cc b/usrp/host/lib/db_wbxng_adf4350_regs.cc index 21d77dcce..aa13d50b9 100644 --- a/usrp/host/lib/db_wbxng_adf4350_regs.cc +++ b/usrp/host/lib/db_wbxng_adf4350_regs.cc @@ -55,8 +55,7 @@ const uint8_t adf4350_regs::s_output_power = 3; /* reg 5 */ const uint8_t adf4350_regs::s_ld_pin_mode = 1; -adf4350_regs::adf4350_regs(adf4350* _adf4350){ - d_adf4350 = _adf4350; +adf4350_regs::adf4350_regs(){ /* reg 0 */ d_int = uint16_t(100); @@ -79,10 +78,10 @@ adf4350_regs::~adf4350_regs(void){ uint32_t adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){ return data << shift; - } +} -void -adf4350_regs::_load_register(uint8_t addr){ +uint32_t +adf4350_regs::compute_register(uint8_t addr){ uint32_t data; switch (addr){ case 0: data = ( @@ -123,8 +122,9 @@ adf4350_regs::_load_register(uint8_t addr){ _reg_shift(s_output_power, 3)); break; case 5: data = ( _reg_shift(s_ld_pin_mode, 22)); break; - default: return; + default: return data; } - /* write the data out to spi */ - d_adf4350->_write(addr, data); + /* return the data to write out to spi */ + return data; } + diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.h b/usrp/host/lib/db_wbxng_adf4350_regs.h index 0018aa07f..33a548e85 100644 --- a/usrp/host/lib/db_wbxng_adf4350_regs.h +++ b/usrp/host/lib/db_wbxng_adf4350_regs.h @@ -29,13 +29,11 @@ class adf4350; class adf4350_regs { public: - adf4350_regs(adf4350* _adf4350); + adf4350_regs(); ~adf4350_regs(); - adf4350* d_adf4350; - uint32_t _reg_shift(uint32_t data, uint32_t shift); - void _load_register(uint8_t addr); + uint32_t compute_register(uint8_t addr); /* reg 0 */ uint16_t d_int; @@ -75,6 +73,11 @@ public: static const uint8_t s_output_power; /* reg 5 */ static const uint8_t s_ld_pin_mode; + +protected: + usrp_basic_sptr d_usrp; + int d_spi_enable; + int d_spi_format; }; #endif /* ADF4350_REGS_H */ diff --git a/usrp/host/lib/usrp_dbid.dat b/usrp/host/lib/usrp_dbid.dat index 7d1e18714..2548d737e 100644 --- a/usrp/host/lib/usrp_dbid.dat +++ b/usrp/host/lib/usrp_dbid.dat @@ -61,6 +61,9 @@ "Flex 1200 Tx MIMO B" 0x002a "Flex 2400 Tx MIMO B" 0x002b +"Flex 2200 Rx MIMO B" 0x002c +"Flex 2200 Tx MIMO B" 0x002d + "Flex 1800 Rx" 0x0030 "Flex 1800 Tx" 0x0031 "Flex 1800 Rx MIMO A" 0x0032 @@ -84,5 +87,7 @@ "XCVR2450 Tx" 0x0060 "XCVR2450 Rx" 0x0061 +"Bitshark Rx" 0x0070 + "Experimental Tx" 0xfffe "Experimental Rx" 0xffff diff --git a/usrp/usrp.pc.in b/usrp/usrp.pc.in index d4794aa6f..3c30de622 100644 --- a/usrp/usrp.pc.in +++ b/usrp/usrp.pc.in @@ -6,6 +6,6 @@ includedir=@includedir@ Name: usrp Description: USRP Client Side C++ interface Requires: @LIBUSB_PKG_CONFIG_NAME@ -Version: @VERSION@ +Version: @LIBVER@ Libs: -L${libdir} -lusrp Cflags: -I${includedir} |