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Diffstat (limited to 'usrp')
-rw-r--r--usrp/host/lib/db_wbxng.cc23
-rw-r--r--usrp/host/lib/db_wbxng_adf4350.cc40
-rw-r--r--usrp/host/lib/db_wbxng_adf4350_regs.cc20
3 files changed, 49 insertions, 34 deletions
diff --git a/usrp/host/lib/db_wbxng.cc b/usrp/host/lib/db_wbxng.cc
index ccad3cb41..1c7b23265 100644
--- a/usrp/host/lib/db_wbxng.cc
+++ b/usrp/host/lib/db_wbxng.cc
@@ -43,10 +43,11 @@ wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which, int _power_on)
@type which: int
*/
+ usrp()->_write_oe(d_which, 0, 0xffff); // turn off all outputs
+
d_first = true;
d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
- usrp()->_write_oe(d_which, 1, 0xffff); // turn off all outputs
_enable_refclk(false); // disable refclk
set_auto_tr(false);
@@ -202,11 +203,14 @@ wbxng_base::set_freq(double freq)
actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
*/
- freq_t int_freq = (freq_t) freq;
+ freq_t int_freq = (freq_t) (freq/1000);
bool ok = d_common->_set_freq(int_freq);
- double freq_result = (double) d_common->_get_freq();
+ double freq_result = (double) d_common->_get_freq()*1000;
struct freq_result_t args = {ok, freq_result};
+ fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
+ int_freq*1000, freq_result, _lock_detect());
+
// Offsetting the LO helps get the Tx carrier leakage out of the way.
// This also ensures that on Rx, we're not getting hosed by the
// FPGA's DC removal loop's time constant. We were seeing a
@@ -287,8 +291,8 @@ wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
d_common = new adf4350(_usrp, d_which, d_spi_enable);
// power up the transmit side, but don't enable the mixer
- usrp()->_write_oe(d_which,(RX_TXN|ENABLE_33|ENABLE_5), 0xffff);
- usrp()->write_io(d_which, (power_on()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->_write_oe(d_which,(PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
//set_lo_offset(4e6);
//set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
@@ -310,7 +314,7 @@ wbxng_base_tx::shutdown()
// do whatever there is to do to shutdown
// Power down and leave the T/R switch in the R position
- usrp()->write_io(d_which, (power_off()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_off()|RX_TXN), (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5));
/*
// Power down VCO/PLL
@@ -352,7 +356,7 @@ wbxng_base_tx::set_enable(bool on)
int v;
int mask = RX_TXN | ENABLE_5 | ENABLE_33;
if(on) {
- v = ENABLE_5 | ENABLE_33;
+ v = PLL_CE | ENABLE_5 | ENABLE_33;
}
else {
v = RX_TXN;
@@ -411,9 +415,8 @@ wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
d_common = new adf4350(_usrp, d_which, d_spi_enable);
- usrp()->_write_oe(d_which, (RX2_RX1N|ENABLE_33|ENABLE_5), 0xffff);
- usrp()->write_io(d_which, (power_on()|RX2_RX1N|ENABLE_33|ENABLE_5),
- (RX2_RX1N|ENABLE_33|ENABLE_5));
+ usrp()->_write_oe(d_which, (RX2_RX1N|ENABLE_33|ENABLE_5), (RX2_RX1N|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (power_on()|RX2_RX1N|ENABLE_33|ENABLE_5), (RX2_RX1N|ENABLE_33|ENABLE_5));
// set up for RX on TX/RX port
select_rx_antenna("TX/RX");
diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc
index a1f024b4f..6e74bf0c1 100644
--- a/usrp/host/lib/db_wbxng_adf4350.cc
+++ b/usrp/host/lib/db_wbxng_adf4350.cc
@@ -13,11 +13,11 @@
//#include "io.h"
//#include "spi.h"
-#define INPUT_REF_FREQ FREQ_C(10e6)
+#define INPUT_REF_FREQ FREQ_C(32e6)
#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
-#define FREQ_C(freq) ((uint32_t)DIV_ROUND(freq, (uint32_t)1000))
+#define FREQ_C(freq) ((uint64_t)DIV_ROUND(freq, (uint64_t)1000))
#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */
-#define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
+#define MIN_INT_DIV uint16_t(300) /* minimum int divider, prescaler 4/5 only */
#define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
#define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */
#define MAX_VCO_FREQ FREQ_C(4.4e9) /* minimum vco freq */
@@ -40,12 +40,23 @@ adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable){
d_regs = new adf4350_regs(this);
/* Outputs */
- d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), 0xffff);
+ d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
/* Initialize the pin levels. */
_enable(true);
/* Initialize the registers. */
- d_regs->_load_register(5);
+ /*
+ timespec t;
+ t.tv_sec = 1;
+ t.tv_nsec = 0;
+ while (1) {
+ */
+ d_regs->_load_register(5);
+ /*
+ nanosleep(&t, NULL);
+ }
+ */
d_regs->_load_register(4);
d_regs->_load_register(3);
d_regs->_load_register(2);
@@ -75,9 +86,9 @@ adf4350::_get_locked(void){
void
adf4350::_enable(bool enable){
if (enable){ /* chip enable */
- d_usrp->write_io(d_which, 1, CE_PIN);
+ d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
}else{
- d_usrp->write_io(d_which, 0, CE_PIN);
+ d_usrp->write_io(d_which, 0, (CE_PIN | PDB_RF_PIN));
}
}
@@ -91,9 +102,10 @@ adf4350::_write(uint8_t addr, uint32_t data){
s[1] = (char)((data >> 16) & 0xff);
s[2] = (char)((data >> 8) & 0xff);
s[3] = (char)(data & 0xff);
- std::string str(s, 3);
+ std::string str(s, 4);
d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
+ fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
/* pulse latch */
//d_usrp->write_io(d_which, 1, LE_PIN);
//d_usrp->write_io(d_which, 0, LE_PIN);
@@ -110,26 +122,26 @@ adf4350::_set_freq(freq_t freq){
d_regs->d_divider_select++; //double the divider
}
/* Ramp up the R divider until the N divider is at least the minimum. */
- d_regs->d_10_bit_r_counter = INPUT_REF_FREQ_2X*MIN_INT_DIV/freq;
+ d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
uint64_t n_mod;
do{
d_regs->d_10_bit_r_counter++;
n_mod = freq;
n_mod *= d_regs->d_10_bit_r_counter;
n_mod *= d_regs->d_mod;
- n_mod /= INPUT_REF_FREQ_2X;
+ n_mod /= INPUT_REF_FREQ;
/* calculate int and frac */
d_regs->d_int = n_mod/d_regs->d_mod;
d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
- /*printf(
+ fprintf(stderr,
"VCO %lu KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n",
freq, d_regs->d_int, d_regs->d_frac,
d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select)
- );*/
+ );
}while(d_regs->d_int < MIN_INT_DIV);
/* calculate the band select so PFD is under 125 KHz */
d_regs->d_8_bit_band_select_clock_divider_value = \
- INPUT_REF_FREQ_2X/(FREQ_C(125e3)*d_regs->d_10_bit_r_counter) + 1;
+ INPUT_REF_FREQ/(FREQ_C(125e3)*d_regs->d_10_bit_r_counter) + 1;
/* load involved registers */
d_regs->_load_register(2);
d_regs->_load_register(4);
@@ -148,7 +160,7 @@ adf4350::_get_freq(void){
temp = d_regs->d_int;
temp *= d_regs->d_mod;
temp += d_regs->d_frac;
- temp *= INPUT_REF_FREQ_2X;
+ temp *= INPUT_REF_FREQ;
temp /= d_regs->d_mod;
temp /= d_regs->d_10_bit_r_counter;
temp /= (1 << d_regs->d_divider_select);
diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.cc b/usrp/host/lib/db_wbxng_adf4350_regs.cc
index 3452663c8..bf39c73ca 100644
--- a/usrp/host/lib/db_wbxng_adf4350_regs.cc
+++ b/usrp/host/lib/db_wbxng_adf4350_regs.cc
@@ -8,13 +8,13 @@
/* reg 0 */
/* reg 1 */
-const uint8_t adf4350_regs::s_prescaler = 1;
+const uint8_t adf4350_regs::s_prescaler = 0;
const uint16_t adf4350_regs::s_phase = 0;
/* reg 2 */
const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0;
-const uint8_t adf4350_regs::s_muxout = 6;
-const uint8_t adf4350_regs::s_reference_doubler = 1;
-const uint8_t adf4350_regs::s_rdiv2 = 0;
+const uint8_t adf4350_regs::s_muxout = 3;
+const uint8_t adf4350_regs::s_reference_doubler = 0;
+const uint8_t adf4350_regs::s_rdiv2 = 1;
const uint8_t adf4350_regs::s_double_buff = 0;
const uint8_t adf4350_regs::s_charge_pump_setting = 7;
const uint8_t adf4350_regs::s_ldf = 0;
@@ -31,11 +31,11 @@ const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0;
const uint8_t adf4350_regs::s_feedback_select = 1;
const uint8_t adf4350_regs::s_vco_power_down = 0;
const uint8_t adf4350_regs::s_mtld = 0;
-const uint8_t adf4350_regs::s_aux_output_select = 0;
-const uint8_t adf4350_regs::s_aux_output_enable = 0;
-const uint8_t adf4350_regs::s_aux_output_power = 0;
-const uint8_t adf4350_regs::s_rf_output_enable = 1;
-const uint8_t adf4350_regs::s_output_power = 1;
+const uint8_t adf4350_regs::s_aux_output_select = 1;
+const uint8_t adf4350_regs::s_aux_output_enable = 1;
+const uint8_t adf4350_regs::s_aux_output_power = 1;
+const uint8_t adf4350_regs::s_rf_output_enable = 0;
+const uint8_t adf4350_regs::s_output_power = 0;
/* reg 5 */
const uint8_t adf4350_regs::s_ld_pin_mode = 1;
@@ -48,7 +48,7 @@ adf4350_regs::adf4350_regs(adf4350* _adf4350){
/* reg 1 */
d_mod = uint16_t(0xfff); /* max fractional accuracy */
/* reg 2 */
- d_10_bit_r_counter = uint16_t(1);
+ d_10_bit_r_counter = uint16_t(2);
/* reg 3 */
/* reg 4 */
d_divider_select = 0;
generated by cgit (git 2.34.1) at 2024-12-20 18:28:38 +0000