diff options
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/fpga/control_lib/fifo_2clock.v | 66 | ||||
| -rw-r--r-- | usrp2/fpga/simple_gemac/simple_gemac_wrapper.v | 22 | ||||
| -rwxr-xr-x | usrp2/fpga/top/u2_core/u2_core.v | 7 |
3 files changed, 22 insertions, 73 deletions
diff --git a/usrp2/fpga/control_lib/fifo_2clock.v b/usrp2/fpga/control_lib/fifo_2clock.v deleted file mode 100644 index 6b1eb607e..000000000 --- a/usrp2/fpga/control_lib/fifo_2clock.v +++ /dev/null @@ -1,66 +0,0 @@ - -module fifo_2clock - #(parameter DWIDTH=32, AWIDTH=9) - (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk, - input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk, - input arst); - - reg [AWIDTH-1:0] wr_addr, rd_addr; - wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk; - wire [AWIDTH-1:0] next_rd_addr; - wire enb_read; - - // Write side management - wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1; - always @(posedge wclk or posedge arst) - if(arst) - wr_addr <= 0; - else if(write) - wr_addr <= next_wr_addr; - assign full = (next_wr_addr == rd_addr_wclk); - - // RAM for data storage. Data out is registered, complicating the - // read side logic - ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram - (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(), - .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) ); - - // Read side management - reg data_valid; - assign empty = ~data_valid; - assign next_rd_addr = rd_addr + data_valid; - assign enb_read = read | ~data_valid; - - always @(posedge rclk or posedge arst) - if(arst) - rd_addr <= 0; - else if(read) - rd_addr <= rd_addr + 1; - - always @(posedge rclk or posedge arst) - if(arst) - data_valid <= 0; - else - if(read & (next_rd_addr == wr_addr_rclk)) - data_valid <= 0; - else if(next_rd_addr != wr_addr_rclk) - data_valid <= 1; - - // Send pointers across clock domains via gray code - gray_send #(.WIDTH(AWIDTH)) send_wr_addr - (.clk_in(wclk),.addr_in(wr_addr), - .clk_out(rclk),.addr_out(wr_addr_rclk) ); - - gray_send #(.WIDTH(AWIDTH)) send_rd_addr - (.clk_in(rclk),.addr_in(rd_addr), - .clk_out(wclk),.addr_out(rd_addr_wclk) ); - - // Generate fullness info, these are approximate and may be delayed - // and are only for higher-level flow control. - // Only full and empty are guaranteed exact. - always @(posedge wclk) - level_wclk <= wr_addr - rd_addr_wclk; - always @(posedge rclk) - level_rclk <= wr_addr_rclk - rd_addr; - -endmodule // fifo_2clock diff --git a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v index b9bc05848..8da77f096 100644 --- a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v @@ -38,7 +38,7 @@ module simple_gemac_wrapper .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), - .pause_req(pause_req), .pause_time(pause_time), .pause_en(1), + .pause_req(pause_req), .pause_time(pause_time), .pause_en(pause_en), .ucast_addr(ucast_addr), .mcast_addr(mcast_addr), .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), .pass_pause(pass_pause), .pass_all(pass_all), @@ -136,9 +136,19 @@ module simple_gemac_wrapper .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); - assign debug = { { tx_ll_data }, - { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, - tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, - { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, - { tx_data} }; + wire [31:0] debug_tx, debug_rx; + + assign debug_tx = { { tx_ll_data }, + { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, + tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, + { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, + { tx_data} }; + assign debug_rx = { { rx_ll_data }, + { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, + rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, + { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]}, + { rx_data} }; + + assign debug = debug_rx; + endmodule // simple_gemac_wrapper diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v index a6596eb90..cd0800afc 100755 --- a/usrp2/fpga/top/u2_core/u2_core.v +++ b/usrp2/fpga/top/u2_core/u2_core.v @@ -669,11 +669,16 @@ module u2_core { s6_adr[7:0] }, { 6'd0, mdio_cpy, MDC } }; */ - +/* assign debug = { { GMII_TXD }, { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, { wr2_flags, rd2_flags }, { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; + */ + assign debug = { { GMII_RXD }, + { 1'd0, debug_mac2[3:0], GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, + { wr2_flags, rd2_flags }, + { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; assign debug_gpio_0 = debug_mac; //eth_mac_debug; assign debug_gpio_1 = 0; |