diff options
Diffstat (limited to 'usrp2/fpga')
| -rw-r--r-- | usrp2/fpga/sdr_lib/dsp_core_rx.v | 8 | ||||
| -rw-r--r-- | usrp2/fpga/sdr_lib/hb_dec.v | 5 | ||||
| -rw-r--r-- | usrp2/fpga/sdr_lib/small_hb_dec.v | 22 |
3 files changed, 24 insertions, 11 deletions
diff --git a/usrp2/fpga/sdr_lib/dsp_core_rx.v b/usrp2/fpga/sdr_lib/dsp_core_rx.v index ee713e4ac..af4f0b9fb 100644 --- a/usrp2/fpga/sdr_lib/dsp_core_rx.v +++ b/usrp2/fpga/sdr_lib/dsp_core_rx.v @@ -139,20 +139,20 @@ module dsp_core_rx always @(posedge clk) strobe_cic_d1 <= strobe_cic; small_hb_dec #(.WIDTH(18)) small_hb_i - (.clk(clk),.rst(rst),.bypass(~enable_hb1), + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1)); small_hb_dec #(.WIDTH(18)) small_hb_q - (.clk(clk),.rst(rst),.bypass(~enable_hb1), + (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1)); wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate}; hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb), + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2)); hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q - (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb), + (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); diff --git a/usrp2/fpga/sdr_lib/hb_dec.v b/usrp2/fpga/sdr_lib/hb_dec.v index b256eb57f..8fb5ba222 100644 --- a/usrp2/fpga/sdr_lib/hb_dec.v +++ b/usrp2/fpga/sdr_lib/hb_dec.v @@ -9,6 +9,7 @@ module hb_dec (input clk, input rst, input bypass, + input run, input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block input stb_in, input [IWIDTH-1:0] data_in, @@ -25,7 +26,7 @@ module hb_dec assign do_mult = 1; always @(posedge clk) - if(rst) + if(rst | ~run) odd <= 0; else if(stb_in) odd <= ~odd; @@ -34,7 +35,7 @@ module hb_dec assign write_even = stb_in & ~odd; always @(posedge clk) - if(rst) + if(rst | ~run) phase <= 0; else if(stb_in & odd) phase <= 1; diff --git a/usrp2/fpga/sdr_lib/small_hb_dec.v b/usrp2/fpga/sdr_lib/small_hb_dec.v index 9957de15a..8519b628a 100644 --- a/usrp2/fpga/sdr_lib/small_hb_dec.v +++ b/usrp2/fpga/sdr_lib/small_hb_dec.v @@ -8,6 +8,7 @@ module small_hb_dec (input clk, input rst, input bypass, + input run, input stb_in, input [WIDTH-1:0] data_in, output reg stb_out, @@ -21,15 +22,26 @@ module small_hb_dec wire go; reg phase, go_d1, go_d2, go_d3, go_d4; always @(posedge clk) - if(rst) + if(rst | ~run) phase <= 0; else if(stb_in_d1) phase <= ~phase; assign go = stb_in_d1 & phase; - always @(posedge clk) go_d1 <= go; - always @(posedge clk) go_d2 <= go_d1; - always @(posedge clk) go_d3 <= go_d2; - always @(posedge clk) go_d4 <= go_d3; + always @(posedge clk) + if(rst | ~run) + begin + go_d1 <= 0; + go_d2 <= 0; + go_d3 <= 0; + go_d4 <= 0; + end + else + begin + go_d1 <= go; + go_d2 <= go_d1; + go_d3 <= go_d2; + go_d4 <= go_d3; + end wire [17:0] coeff_a = -10690; wire [17:0] coeff_b = 75809; |