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-rwxr-xr-xusrp2/fpga/top/u2_core/u2_core.v4
1 files changed, 3 insertions, 1 deletions
diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
index 1f78f6d3d..03016e9b3 100755
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -525,9 +525,11 @@ module u2_core
(.clk(wb_clk),.rst(wb_rst),
.sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
.wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
- .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o),.wb_dat_o(sd_dat_i),
+ .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]),
.wb_ack_o(sd_ack) );
+ assign sd_dat_i[31:8] = 0;
+
// /////////////////////////////////////////////////////////////////////////
// DSP
wire [31:0] sample_rx, sample_tx;