2 files changed, 28 insertions, 77 deletions

diff --git a/usrp2/fpga/serdes/serdes_rx.v b/usrp2/fpga/serdes/serdes_rx.v
index aaca94ff1..afefccaa1 100644
--- a/usrp2/fpga/serdes/serdes_rx.v
+++ b/usrp2/fpga/serdes/serdes_rx.v
@@ -70,7 +70,7 @@ module serdes_rx
    
    reg [31:0]  line_i;
    reg 	       sop_i, eop_i, error_i;
-   wire        error_o, sop_o, eop_o, write, read, empty, full;
+   wire        error_o, sop_o, eop_o, write;
    reg [15:0]  halfline;
    reg [8:0]   holder;
    wire [31:0] line_o;
@@ -82,14 +82,10 @@ module serdes_rx
    reg 	       write_d;
 
    wire        rst_rxclk;
+   wire        have_space;
+
    oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk));
 
-   /*
-   ss_rcvr #(.WIDTH(18)) ss_rcvr
-     (.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst),
-      .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(even_data),
-      .clock_present());
-   */
    assign      even_data = {ser_rkmsb,ser_rklsb,ser_r};
    
    always @(posedge ser_rx_clk)
@@ -171,7 +167,7 @@ module serdes_rx
 	   if(chosen_data[17:16] == 0)
 	     begin
 		line_i <= {chosen_data[15:0],halfline};
-		if(full)  // No space to write to!  Should have been avoided by flow control
+		if(~have_space)  // No space to write to!  Should have been avoided by flow control
 		  state <= ERROR;
 		else
 		  begin
@@ -204,7 +200,7 @@ module serdes_rx
 	   if(chosen_data[17:16] == 0)
 	     begin
 		line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline};
-		if(full)  // No space to write to!
+		if(~have_space)  // No space to write to!
 		  state <= ERROR;
 		else
 		  begin
@@ -220,7 +216,7 @@ module serdes_rx
 	 CRC_CHECK :
 	   if(chosen_data[17:0] == {2'b00,CRC})
 	     begin
-		if(full)
+		if(~have_space)
 		  state <= ERROR;
 		else
 		  begin
@@ -236,7 +232,7 @@ module serdes_rx
 	 ERROR :
 	   begin
 	      error_i <= 1;
-	      if(~full)
+	      if(have_space)
 		state <= IDLE;
 	   end
 	 DONE :
@@ -263,62 +259,19 @@ module serdes_rx
      else write_d <= write_pre;
 
    // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
-   assign write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK));
-
-
-//`define CASC 1
-`define MYFIFO 1   
-//`define XILFIFO 1
+   assign write = eop_i | (error_i & have_space) | (write_d & (state != CRC_CHECK));
 
-`ifdef CASC   
-   cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
-     (.clk(clk),.rst(rst),.clear(0),
-      .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
-      .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
-      .space(fifo_space),.occupied(fifo_occupied) );
-   assign fifo_full = full;
-   assign fifo_empty = empty;
-`endif
-
-`ifdef MYFIFO
-   wire [FIFOSIZE-1:0] level;
-    fifo_2clock_casc #(.DWIDTH(35),.AWIDTH(FIFOSIZE)) serdes_rx_fifo
+   fifo_2clock_cascade #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
      (.arst(rst),
-      .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
-      .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
-      .level_rclk(level) );
-   assign 	       fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - 
-		       {{(16-FIFOSIZE){1'b0}},level};
-   assign 	       fifo_occupied = { {(16-FIFOSIZE){1'b0}} ,level};
-   assign 	       fifo_full = full;   // Note -- fifo_full is in the wrong clock domain
-   assign 	       fifo_empty = empty;
-`endif
+      .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), 
+      .src_rdy_i(write), .dst_rdy_o(have_space), .space(fifo_space), 
+      .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), 
+      .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .occupied(fifo_occupied) );
 
-`ifdef XILFIFO
-   wire [FIFOSIZE-1:0] level;
-   fifo_generator_v4_1 ser_rx_fifo
-     (.din({error_i,sop_i,eop_i,line_i}),
-      .rd_clk(clk),
-      .rd_en(read),
-      .rst(rst),
-      .wr_clk(ser_rx_clk),
-      .wr_en(write),
-      .dout({error_o,sop_o,eop_o,line_o}),
-      .empty(empty),
-      .full(full),
-      .rd_data_count(level),
-      .wr_data_count() );
-   assign 	       fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - 
-		       {{(16-FIFOSIZE){1'b0}},level};
-   assign 	       fifo_occupied  = { {(16-FIFOSIZE){1'b0}}, level };
-   assign 	       fifo_full      = full;   // Note -- fifo_full is in the wrong clock domain
-   assign 	       fifo_empty     = empty;
-`endif //  `ifdef XILFIFO
-   
+   assign 	       fifo_full = ~have_space;   // Note -- in the wrong clock domain
+   assign 	       fifo_empty = ~wr_ready_o;
    
    // Internal FIFO to Buffer interface
-   assign read 			      = wr_ready_i & wr_ready_o;
-   assign wr_ready_o 		      = ~empty;
    assign wr_dat_o 		      = line_o;
    assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o };
    
@@ -334,6 +287,6 @@ module serdes_rx
    always @(posedge clk)
      serdes_link_up <= &slu_reg[3:1];
    
-   assign      debug = { full, empty, odd, sop_i, eop_i, error_i, state[2:0] };
+   assign      debug = { have_space, wr_ready_o, odd, sop_i, eop_i, error_i, state[2:0] };
    
 endmodule // serdes_rx
diff --git a/usrp2/fpga/serdes/serdes_tx.v b/usrp2/fpga/serdes/serdes_tx.v
index b6f19370e..c74414e92 100644
--- a/usrp2/fpga/serdes/serdes_tx.v
+++ b/usrp2/fpga/serdes/serdes_tx.v
@@ -77,25 +77,23 @@ module serdes_tx
    reg [3:0]   wait_count;
    
    // Internal FIFO, size 9 is 2K, size 10 is 4K bytes
-   wire        sop_o, eop_o, write, full, read, empty;
+   wire        sop_o, eop_o;
    wire [31:0] data_o;
-   reg 	       xfer_active;
 
    wire        rd_sop_i  = rd_flags_i[0];
    wire        rd_eop_i  = rd_flags_i[1];
    wire [1:0]  rd_occ_i = rd_flags_i[3:2];  // Unused
-   
-   cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
-     (.clk(clk),.rst(rst),.clear(0),
-      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
-      .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty),
-      .space(), .occupied(fifo_occupied) );
-   assign      fifo_full   = full;
-   assign      fifo_empty  = empty;
-
-   assign write 	   = rd_ready_i & rd_ready_o;
-   assign rd_ready_o 	   = ~full;
 
+   wire        have_data, empty;
+   fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
+     (.clk(clk),.reset(rst),.clear(0),
+      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o),
+      .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data),
+      .space(), .occupied(fifo_occupied) );
+   
+   assign fifo_full   = ~rd_ready_o;
+   assign empty       = ~have_data;
+   assign fifo_empty  = empty;
    
    // FIXME Implement flow control   
    reg [15:0]  second_word;
@@ -182,7 +180,7 @@ module serdes_tx
    
    CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC);
 
-   assign debug = { 26'd0, full, empty, xfer_active, state[2:0] };
+   assign debug = { 28'd0, state[2:0] };
    
 endmodule // serdes_tx