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-rw-r--r--usrp2/fpga/eth/rtl/verilog/MAC_top.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_top.v b/usrp2/fpga/eth/rtl/verilog/MAC_top.v
index d93b287ce..13f17aa13 100644
--- a/usrp2/fpga/eth/rtl/verilog/MAC_top.v
+++ b/usrp2/fpga/eth/rtl/verilog/MAC_top.v
@@ -342,7 +342,7 @@ module MAC_top
.xoff_gen_complete (xoff_gen_complete),
.xon_gen_complete(xon_gen_complete)
);
-
+/*
RMON U_RMON(
.Clk ( CLK_I ),
.Reset ( RST_I ),
@@ -365,7 +365,7 @@ module MAC_top
.CPU_rd_grant ( CPU_rd_grant ),
.CPU_rd_dout ( CPU_rd_dout )
);
-
+*/
Phy_int U_Phy_int(
.rst_mac_rx ( rst_mac_rx ),
.rst_mac_tx ( rst_mac_tx ),