diff options
Diffstat (limited to 'usrp2/fpga/eth/bench/verilog/jumbos.scr')
| -rw-r--r-- | usrp2/fpga/eth/bench/verilog/jumbos.scr | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/usrp2/fpga/eth/bench/verilog/jumbos.scr b/usrp2/fpga/eth/bench/verilog/jumbos.scr deleted file mode 100644 index f48870bd5..000000000 --- a/usrp2/fpga/eth/bench/verilog/jumbos.scr +++ /dev/null @@ -1,27 +0,0 @@ -// This test performs transmission & reception of several Jumbo-frames of ~2Kbytes each
-// At the same time it demonstrates the wire-speed capabilities of the core
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 2047-byte frame 3 times - and expect them to be received again!
-20 07 ff 00 03
-// Transmit a 2048-byte frame 3 times - and expect them to be received again!
-20 08 00 00 03
-// Transmit a 2049-byte frame 3 times - and expect them to be received again!
-20 08 01 00 03
-// Transmit a 2050-byte frame 3 times - and expect them to be received again!
-20 08 02 00 03
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
|