1 files changed, 21 insertions, 0 deletions
diff --git a/usrp2/fpga/control_lib/srl.v b/usrp2/fpga/control_lib/srl.v
new file mode 100644
index 000000000..fa28c7669
--- /dev/null
+++ b/usrp2/fpga/control_lib/srl.v
@@ -0,0 +1,21 @@
+
+module srl
+  #(parameter WIDTH=18)
+    (input clk,
+     input write,
+     input [WIDTH-1:0] in,
+     input [3:0] addr,
+     output [WIDTH-1:0] out);
+   
+   genvar 		i;
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl
+	   SRL16E
+	     srl16e(.Q(out[i]),
+		    .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
+		    .CE(write),.CLK(clk),.D(in[i]));
+	end
+   endgenerate
+
+endmodule // srl