diff options
Diffstat (limited to 'usrp2/fpga/control_lib/newfifo/fifo_2clock.v')
| -rw-r--r-- | usrp2/fpga/control_lib/newfifo/fifo_2clock.v | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v index 40c479db7..2ada39fb0 100644 --- a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v +++ b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v @@ -2,26 +2,39 @@ // FIXME ignores the AWIDTH (fifo size) parameter module fifo_2clock - #(parameter WIDTH=32, SIZE=9) + #(parameter WIDTH=36, SIZE=6) (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input arst); - wire [SIZE-1:0] level_rclk, level_wclk; - wire full, empty, write, read; + wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels + wire full, empty, write, read; assign dst_rdy_o = ~full; assign src_rdy_o = ~empty; assign write = src_rdy_i & dst_rdy_o; assign read = src_rdy_o & dst_rdy_i; - - fifo_xlnx_512x36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - assign occupied = {{(16-SIZE){1'b0}},level_rclk}; - assign space = ((1<<SIZE)-1)-level_wclk; + generate + if(SIZE==9) + fifo_xlnx_512x36_2clk mac_tx_fifo_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==11) + fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==6) + fifo_xlnx_64x36_2clk mac_tx_fifo_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + endgenerate + + assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; + assign space = ((1<<SIZE)+1)-level_wclk; endmodule // fifo_2clock |