diff options
Diffstat (limited to 'usrp2/firmware')
| -rw-r--r-- | usrp2/firmware/apps/.gitignore | 1 | ||||
| -rw-r--r-- | usrp2/firmware/apps/Makefile.am | 4 | ||||
| -rw-r--r-- | usrp2/firmware/lib/Makefile.am | 46 | ||||
| -rw-r--r-- | usrp2/firmware/lib/adf4350.c | 209 | ||||
| -rw-r--r-- | usrp2/firmware/lib/adf4350.h | 40 | ||||
| -rw-r--r-- | usrp2/firmware/lib/adf4350_regs.c | 103 | ||||
| -rw-r--r-- | usrp2/firmware/lib/adf4350_regs.h | 29 | ||||
| -rw-r--r-- | usrp2/firmware/lib/db_init.c | 2 | ||||
| -rw-r--r-- | usrp2/firmware/lib/db_init_wbx.c | 397 | ||||
| -rw-r--r-- | usrp2/firmware/lib/db_wbxng.c | 214 | ||||
| -rw-r--r-- | usrp2/firmware/lib/db_wbxng.h | 74 |
11 files changed, 1117 insertions, 2 deletions
diff --git a/usrp2/firmware/apps/.gitignore b/usrp2/firmware/apps/.gitignore index b8ab0dc8d..855a28a47 100644 --- a/usrp2/firmware/apps/.gitignore +++ b/usrp2/firmware/apps/.gitignore @@ -63,6 +63,7 @@ /tx_only_v2 /rx_only_v2 /txrx +/txrx_wbx /eth_serdes /serdes_txrx /set_hw_rev diff --git a/usrp2/firmware/apps/Makefile.am b/usrp2/firmware/apps/Makefile.am index b809039d0..045a05ab4 100644 --- a/usrp2/firmware/apps/Makefile.am +++ b/usrp2/firmware/apps/Makefile.am @@ -45,6 +45,7 @@ noinst_PROGRAMS = \ timer_test \ tx_standalone \ txrx \ + txrx_wbx \ factory_test \ burnrev30 \ burnrev31 \ @@ -61,12 +62,15 @@ noinst_PROGRAMS = \ # tx_drop_rate_limited_SOURCES = tx_drop_rate_limited.c app_common.c # tx_drop2_SOURCES = tx_drop2.c app_common.c txrx_SOURCES = txrx.c app_common_v2.c +txrx_wbx_SOURCES = txrx.c app_common_v2.c factory_test_SOURCES = factory_test.c app_common_v2.c eth_serdes_SOURCES = eth_serdes.c app_passthru_v2.c serdes_txrx_SOURCES = serdes_txrx.c app_common_v2.c mimo_tx_SOURCES = mimo_tx.c mimo_app_common_v2.c mimo_tx_slave_SOURCES = mimo_tx_slave.c app_common_v2.c +txrx_wbx_LDADD = ../lib/libu2fw_wbx.a + noinst_HEADERS = \ app_common_v2.h \ app_passthru_v2.h \ diff --git a/usrp2/firmware/lib/Makefile.am b/usrp2/firmware/lib/Makefile.am index 37c74c91e..8b7762d40 100644 --- a/usrp2/firmware/lib/Makefile.am +++ b/usrp2/firmware/lib/Makefile.am @@ -18,22 +18,25 @@ include $(top_srcdir)/Makefile.common noinst_LIBRARIES = \ - libu2fw.a + libu2fw.a \ + libu2fw_wbx.a libu2fw_a_SOURCES = \ abort.c \ ad9510.c \ + adf4350.c \ + adf4350_regs.c \ ad9777.c \ bsm12.c \ buffer_pool.c \ clocks.c \ db_basic.c \ db_dbsrx.c \ - db_init.c \ db_rfx.c \ db_tvrx.c \ db_xcvr2450.c \ + db_init.c \ dbsm.c \ eeprom.c \ ethernet.c \ @@ -59,9 +62,47 @@ libu2fw_a_SOURCES = \ spi.c \ u2_init.c +libu2fw_wbx_a_SOURCES = \ + abort.c \ + ad9510.c \ + adf4350.c \ + adf4350_regs.c \ + ad9777.c \ + bsm12.c \ + buffer_pool.c \ + clocks.c \ + db_basic.c \ + db_wbxng.c \ + db_init_wbx.c \ + dbsm.c \ + eeprom.c \ + ethernet.c \ + eth_mac.c \ + _exit.c \ + exit.c \ + hal_io.c \ + hal_uart.c \ + i2c.c \ + lsadc.c \ + lsdac.c \ + mdelay.c \ + memcpy_wa.c \ + memset_wa.c \ + nonstdio.c \ + pic.c \ + print_mac_addr.c \ + print_rmon_regs.c \ + print_fxpt.c \ + print_buffer.c \ + printf.c \ + sd.c \ + spi.c \ + u2_init.c noinst_HEADERS = \ ad9510.h \ + adf4350.h \ + adf4350_regs.h \ ad9777.h \ ad9777_regs.h \ bool.h \ @@ -70,6 +111,7 @@ noinst_HEADERS = \ clocks.h \ db.h \ db_base.h \ + db_wbxng.h \ dbsm.h \ eth_mac.h \ eth_mac_regs.h \ diff --git a/usrp2/firmware/lib/adf4350.c b/usrp2/firmware/lib/adf4350.c new file mode 100644 index 000000000..0725c9337 --- /dev/null +++ b/usrp2/firmware/lib/adf4350.c @@ -0,0 +1,209 @@ +/* + * Copyright 2010 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include "adf4350.h" +#include "adf4350_regs.h" +#include "db_wbxng.h" +#include <spi.h> +#include <hal_io.h> +#include <stdio.h> +#include <stdint.h> + +#define INPUT_REF_FREQ U2_DOUBLE_TO_FXPT_FREQ(50e6) +#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */ +#define MAX_RF_DIV UINT8_C(16) /* max rf divider, divides rf output */ +#define MIN_VCO_FREQ U2_DOUBLE_TO_FXPT_FREQ(2.2e9) /* minimum vco freq */ +#define MAX_VCO_FREQ U2_DOUBLE_TO_FXPT_FREQ(4.4e9) /* minimum vco freq */ +#define MAX_FREQ MAX_VCO_FREQ /* upper bound freq (rf div = 1) */ +#define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV) /* calculated lower bound freq */ + +u2_fxpt_freq_t adf4350_get_max_freq(void){ + return MAX_FREQ; +} + +u2_fxpt_freq_t adf4350_get_min_freq(void){ + return MIN_FREQ; +} + +void adf4350_init(struct db_base *dbb){ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + /* Initialize the pin levels. */ + hal_gpio_write( db->base.is_tx ? GPIO_TX_BANK : GPIO_RX_BANK, PLL_CE, PLL_CE ); + adf4350_enable(true, dbb); + /* Initialize the registers. */ + adf4350_load_register(5, dbb); + adf4350_load_register(4, dbb); + adf4350_load_register(3, dbb); + adf4350_load_register(2, dbb); + adf4350_load_register(1, dbb); + adf4350_load_register(0, dbb); +} + +/* +void adf4350_update(void){ + // mirror the lock detect pin to the led debug + if (adf4350_get_locked()){ + io_set_pin(led_pin); + }else{ + io_clear_pin(led_pin); + } +} +*/ + +bool adf4350_get_locked(struct db_base *dbb){ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + int pins; + pins = hal_gpio_read( db->base.is_tx ? GPIO_TX_BANK : GPIO_RX_BANK ); + if(pins & PLL_LOCK_DETECT) + return true; + return false; +} + +void adf4350_enable(bool enable, struct db_base *dbb){ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + if (enable){ /* chip enable */ + hal_gpio_write( db->base.is_tx ? GPIO_TX_BANK : GPIO_RX_BANK, PLL_PDBRF, PLL_PDBRF ); + }else{ + hal_gpio_write( db->base.is_tx ? GPIO_TX_BANK : GPIO_RX_BANK, 0, PLL_PDBRF ); + } +} + +void adf4350_write(uint8_t addr, uint32_t data, struct db_base *dbb){ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + //printf("SPI write ADDR 0x%x, WORD 0x%x\n", (int) (addr), (int) (data)); + data |= addr; + spi_transact(SPI_TXONLY,db->common.spi_mask,data,32,SPIF_PUSH_FALL); + //spi_read_write(clk_pin, data_pin, ld_pin, &data, 32); + /* pulse latch */ + //io_set_pin(le_pin); + //io_clear_pin(le_pin); +} + +bool adf4350_set_freq(u2_fxpt_freq_t freq, struct db_base *dbb){ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + /* Set the frequency by setting int, frac, mod, r, div */ + if (freq > MAX_FREQ || freq < MIN_FREQ) return false; + + /* Set the prescaler and the min N based on the freq. */ + uint16_t min_int_div; + if (freq > U2_DOUBLE_TO_FXPT_FREQ(3e9) ){ + db->common.adf4350_regs_prescaler = (uint8_t) 1; + min_int_div = UINT16_C(75); + }else{ + db->common.adf4350_regs_prescaler = (uint8_t) 0; + min_int_div = UINT16_C(23); + } + + /* Ramp up the RF divider until the VCO is within range. */ + db->common.adf4350_regs_divider_select = (uint8_t) 0; + while (freq < MIN_VCO_FREQ){ + freq <<= 1; //double the freq + db->common.adf4350_regs_divider_select++; //double the divider + } + + /* Ramp up the R divider until the N divider is at least the minimum. */ + db->common.adf4350_regs_10_bit_r_counter = (uint16_t) (DIV_ROUND((INPUT_REF_FREQ*min_int_div), freq)); + //printf("Initial R setting: %u, MIN_INT: %u\n", db->common.adf4350_regs_10_bit_r_counter, min_int_div); + if (db->common.adf4350_regs_10_bit_r_counter * U2_DOUBLE_TO_FXPT_FREQ(32e6) < INPUT_REF_FREQ){ + db->common.adf4350_regs_10_bit_r_counter = (uint16_t) (DIV_ROUND(INPUT_REF_FREQ, U2_DOUBLE_TO_FXPT_FREQ(32e6))); + //printf("Updating R setting: %u, MIN_INT: %u\n", db->common.adf4350_regs_10_bit_r_counter, min_int_div); + } + + db->common.adf4350_regs_10_bit_r_counter--; + //db->common.adf4350_regs_10_bit_r_counter=1; + + do{ + db->common.adf4350_regs_10_bit_r_counter++; + /* throw out some fractional bits in freq to avoid overflow */ + u2_fxpt_freq_t some_frac_freq = (U2_DOUBLE_TO_FXPT_FREQ(1.0)/db->common.adf4350_regs_mod); + uint64_t n_mod = DIV_ROUND(freq, some_frac_freq); + n_mod *= db->common.adf4350_regs_10_bit_r_counter; + n_mod *= db->common.adf4350_regs_mod; + n_mod = DIV_ROUND(n_mod, DIV_ROUND(INPUT_REF_FREQ, some_frac_freq)); + /* calculate int and frac: regs_mod is a power of 2, this will optimize to a bitwise operation */ + db->common.adf4350_regs_int = (uint16_t) (n_mod/db->common.adf4350_regs_mod); + db->common.adf4350_regs_frac = (uint16_t) (n_mod%db->common.adf4350_regs_mod); + //printf("Int %u < Min %u\n", db->common.adf4350_regs_int, min_int_div); + }while(db->common.adf4350_regs_int < min_int_div); + + /* calculate the band select so PFD is under 125 KHz */ + db->common.adf4350_regs_8_bit_band_select_clock_divider_value = \ + (uint8_t) (INPUT_REF_FREQ/(U2_DOUBLE_TO_FXPT_FREQ(30e3)*db->common.adf4350_regs_10_bit_r_counter)) + 1; + + /* + printf( + "VCO %u KHz, Int %u, Frac %u, Mod %u, R %u, Div %u, BandSelect %u\n", + (uint32_t) ((freq >> U2_FPF_RP)/1000), + (uint32_t) db->common.adf4350_regs_int, + (uint32_t) db->common.adf4350_regs_frac, + (uint32_t) db->common.adf4350_regs_mod, + (uint32_t) db->common.adf4350_regs_10_bit_r_counter, + (uint32_t) (1 << db->common.adf4350_regs_divider_select), + (uint32_t) db->common.adf4350_regs_8_bit_band_select_clock_divider_value + ); + */ + + /* load involved registers */ + adf4350_load_register(5, dbb); + adf4350_load_register(3, dbb); + adf4350_load_register(1, dbb); + adf4350_load_register(2, dbb); + adf4350_load_register(4, dbb); + adf4350_load_register(0, dbb); /* register 0 must be last */ + return true; +} + +u2_fxpt_freq_t adf4350_get_freq(struct db_base *dbb){ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + /* Calculate the freq from int, frac, mod, ref, r, div: + * freq = (int + frac/mod) * (ref/r) + * Keep precision by doing multiplies first: + * freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div) + */ + uint64_t temp; + temp = (uint64_t) db->common.adf4350_regs_int; + temp *= (uint64_t) db->common.adf4350_regs_mod; + temp += (uint64_t) db->common.adf4350_regs_frac; + temp *= (uint64_t) (INPUT_REF_FREQ >> U2_FPF_RP); + temp /= (uint64_t) db->common.adf4350_regs_mod; + temp /= (uint64_t) db->common.adf4350_regs_10_bit_r_counter; + temp /= (uint64_t) (1 << db->common.adf4350_regs_divider_select); + + /* Shift 1Hz Radix Point for u2_fxpt_freq_t */ + temp = temp << U2_FPF_RP; + + /* + printf( + "Got Freq %u KHz, Int %u, Frac %u, Mod %u, R %u, Div %u\n", + (uint32_t) ((temp >> U2_FPF_RP)/1000), + (uint32_t) db->common.adf4350_regs_int, + (uint32_t) db->common.adf4350_regs_frac, + (uint32_t) db->common.adf4350_regs_mod, + (uint32_t) db->common.adf4350_regs_10_bit_r_counter, + (uint32_t) (1 << db->common.adf4350_regs_divider_select) + ); + */ + + return (u2_fxpt_freq_t) (temp); +} diff --git a/usrp2/firmware/lib/adf4350.h b/usrp2/firmware/lib/adf4350.h new file mode 100644 index 000000000..3c66ec344 --- /dev/null +++ b/usrp2/firmware/lib/adf4350.h @@ -0,0 +1,40 @@ +/* + * Copyright 2010 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef ADF4350_H +#define ADF4350_H + +#include <db_base.h> +#include <stdbool.h> +#include <stdint.h> + +#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom)) +#define UINT8_C(num) ((uint8_t) (num)) +#define UINT16_C(num) ((uint16_t) (num)) + +void adf4350_init(struct db_base *dbb); +//void adf4350_update(void); +bool adf4350_get_locked(struct db_base *dbb); +void adf4350_enable(bool enable, struct db_base *dbb); +void adf4350_write(uint8_t addr, uint32_t data, struct db_base *dbb); +bool adf4350_set_freq(u2_fxpt_freq_t freq, struct db_base *dbb); +u2_fxpt_freq_t adf4350_get_freq(struct db_base *dbb); +u2_fxpt_freq_t adf4350_get_max_freq(void); +u2_fxpt_freq_t adf4350_get_min_freq(void); + +#endif /* ADF4350_H */ diff --git a/usrp2/firmware/lib/adf4350_regs.c b/usrp2/firmware/lib/adf4350_regs.c new file mode 100644 index 000000000..e2740d3ab --- /dev/null +++ b/usrp2/firmware/lib/adf4350_regs.c @@ -0,0 +1,103 @@ +/* + * Copyright 2010 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include "adf4350_regs.h" +#include "adf4350.h" +#include "db_wbxng.h" + +#define _REG_SHIFT(reg, shift) (((uint32_t)(reg)) << (shift)) + +/* reg 0 */ +/* reg 1 */ +static const uint16_t adf4350_regs_phase = 0; /* 0 */ +/* reg 2 */ +static const uint8_t adf4350_regs_low_noise_and_low_spur_modes = 3; /* low noise mode */ +static const uint8_t adf4350_regs_muxout = 3; /* digital lock detect */ +static const uint8_t adf4350_regs_reference_doubler = 0; /* disabled */ +static const uint8_t adf4350_regs_rdiv2 = 1; /* disabled */ +static const uint8_t adf4350_regs_double_buff = 0; /* disabled */ +static const uint8_t adf4350_regs_charge_pump_setting = 5; /* 2.50 mA */ +static const uint8_t adf4350_regs_ldf = 0; /* frac-n */ +static const uint8_t adf4350_regs_ldp = 0; /* 10 ns */ +static const uint8_t adf4350_regs_pd_polarity = 1; /* positive */ +static const uint8_t adf4350_regs_power_down = 0; /* disabled */ +static const uint8_t adf4350_regs_cp_three_state = 0; /* disabled */ +static const uint8_t adf4350_regs_counter_reset = 0; /* disabled */ +/* reg 3 */ +static const uint8_t adf4350_regs_csr = 0; /* disabled */ +static const uint8_t adf4350_regs_clk_div_mode = 0; /* clock divider off */ +static const uint16_t adf4350_regs_12_bit_clock_divider_value = 0; /* 0 */ +/* reg 4 */ +static const uint8_t adf4350_regs_feedback_select = 1; /* fundamental */ +static const uint8_t adf4350_regs_vco_power_down = 0; /* vco powered up */ +static const uint8_t adf4350_regs_mtld = 0; /* mute disabled */ +static const uint8_t adf4350_regs_aux_output_select = 1; /* divided output */ +static const uint8_t adf4350_regs_aux_output_enable = 1; /* disabled */ +static const uint8_t adf4350_regs_aux_output_power = 0; /* -4 */ +static const uint8_t adf4350_regs_rf_output_enable = 1; /* enabled */ +static const uint8_t adf4350_regs_output_power = 3; /* -1 */ +/* reg 5 */ +static const uint8_t adf4350_regs_ld_pin_mode = 1; /* digital lock detect */ + +void adf4350_load_register(uint8_t addr, struct db_base *dbb){ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + uint32_t data; + switch (addr){ + case 0: data = ( + _REG_SHIFT(db->common.adf4350_regs_int, 15) | + _REG_SHIFT(db->common.adf4350_regs_frac, 3)); break; + case 1: data = ( + _REG_SHIFT(db->common.adf4350_regs_prescaler, 27) | + _REG_SHIFT(adf4350_regs_phase, 15) | + _REG_SHIFT(db->common.adf4350_regs_mod, 3)); break; + case 2: data = ( + _REG_SHIFT(adf4350_regs_low_noise_and_low_spur_modes, 29) | + _REG_SHIFT(adf4350_regs_muxout, 26) | + _REG_SHIFT(adf4350_regs_reference_doubler, 25) | + _REG_SHIFT(adf4350_regs_rdiv2, 24) | + _REG_SHIFT(db->common.adf4350_regs_10_bit_r_counter, 14) | + _REG_SHIFT(adf4350_regs_double_buff, 13) | + _REG_SHIFT(adf4350_regs_charge_pump_setting, 9) | + _REG_SHIFT(adf4350_regs_ldf, 8) | + _REG_SHIFT(adf4350_regs_ldp, 7) | + _REG_SHIFT(adf4350_regs_pd_polarity, 6) | + _REG_SHIFT(adf4350_regs_power_down, 5) | + _REG_SHIFT(adf4350_regs_cp_three_state, 4) | + _REG_SHIFT(adf4350_regs_counter_reset, 3)); break; + case 3: data = ( + _REG_SHIFT(adf4350_regs_csr, 18) | + _REG_SHIFT(adf4350_regs_clk_div_mode, 15) | + _REG_SHIFT(adf4350_regs_12_bit_clock_divider_value, 3)); break; + case 4: data = ( + _REG_SHIFT(adf4350_regs_feedback_select, 23) | + _REG_SHIFT(db->common.adf4350_regs_divider_select, 20) | + _REG_SHIFT(db->common.adf4350_regs_8_bit_band_select_clock_divider_value, 12) | + _REG_SHIFT(adf4350_regs_vco_power_down, 11) | + _REG_SHIFT(adf4350_regs_mtld, 10) | + _REG_SHIFT(adf4350_regs_aux_output_select, 9) | + _REG_SHIFT(adf4350_regs_aux_output_enable, 8) | + _REG_SHIFT(adf4350_regs_aux_output_power, 6) | + _REG_SHIFT(adf4350_regs_rf_output_enable, 5) | + _REG_SHIFT(adf4350_regs_output_power, 3)); break; + case 5: data = ( + _REG_SHIFT(adf4350_regs_ld_pin_mode, 22)); break; + default: return; + } + /* write the data out to spi */ + adf4350_write(addr, data, dbb); +} diff --git a/usrp2/firmware/lib/adf4350_regs.h b/usrp2/firmware/lib/adf4350_regs.h new file mode 100644 index 000000000..f7c160f6f --- /dev/null +++ b/usrp2/firmware/lib/adf4350_regs.h @@ -0,0 +1,29 @@ +/* + * Copyright 2010 Free Software Foundation, Inc. + * + * Copyright 2010 Ettus Research LLC + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef ADF4350_REGS_H +#define ADF4350_REGS_H + +#include <db_base.h> +#include <stdint.h> + +void adf4350_load_register(uint8_t addr, struct db_base *dbb); + +#endif /* ADF4350_REGS_H */ diff --git a/usrp2/firmware/lib/db_init.c b/usrp2/firmware/lib/db_init.c index a0bfc5cfb..5104f3ce0 100644 --- a/usrp2/firmware/lib/db_init.c +++ b/usrp2/firmware/lib/db_init.c @@ -45,6 +45,8 @@ extern struct db_base db_rfx_1800_tx; extern struct db_base db_rfx_1800_rx; extern struct db_base db_rfx_2400_tx; extern struct db_base db_rfx_2400_rx; +extern struct db_base db_wbxng_rx; +extern struct db_base db_wbxng_tx; extern struct db_base db_tvrx1; extern struct db_base db_tvrx2; extern struct db_base db_tvrx3; diff --git a/usrp2/firmware/lib/db_init_wbx.c b/usrp2/firmware/lib/db_init_wbx.c new file mode 100644 index 000000000..d7fa20cf9 --- /dev/null +++ b/usrp2/firmware/lib/db_init_wbx.c @@ -0,0 +1,397 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008,2009 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include <memory_map.h> +#include <i2c.h> +#include <usrp2_i2c_addr.h> +#include <string.h> +#include <stdio.h> +#include <db.h> +#include <db_base.h> +#include <hal_io.h> +#include <nonstdio.h> + + +struct db_base *tx_dboard; // the tx daughterboard that's installed +struct db_base *rx_dboard; // the rx daughterboard that's installed + +extern struct db_base db_basic_tx; +extern struct db_base db_basic_rx; +extern struct db_base db_lf_tx; +extern struct db_base db_lf_rx; +extern struct db_base db_wbxng_rx; +extern struct db_base db_wbxng_tx; + +struct db_base *all_dboards[] = { + &db_basic_tx, + &db_basic_rx, + &db_lf_tx, + &db_lf_rx, + &db_wbxng_rx, + &db_wbxng_tx, + 0 +}; + + +typedef enum { UDBE_OK, UDBE_NO_EEPROM, UDBE_INVALID_EEPROM } usrp_dbeeprom_status_t; + +static usrp_dbeeprom_status_t +read_raw_dboard_eeprom (unsigned char *buf, int i2c_addr) +{ + if (!eeprom_read (i2c_addr, 0, buf, DB_EEPROM_CLEN)) + return UDBE_NO_EEPROM; + + if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE) + return UDBE_INVALID_EEPROM; + + int sum = 0; + unsigned int i; + for (i = 0; i < DB_EEPROM_CLEN; i++) + sum += buf[i]; + + if ((sum & 0xff) != 0) + return UDBE_INVALID_EEPROM; + + return UDBE_OK; +} + + +/* + * Return DBID, -1 <none> or -2 <invalid eeprom contents> + */ +int +read_dboard_eeprom(int i2c_addr) +{ + unsigned char buf[DB_EEPROM_CLEN]; + + usrp_dbeeprom_status_t s = read_raw_dboard_eeprom (buf, i2c_addr); + + //printf("\nread_raw_dboard_eeprom: %d\n", s); + + switch (s){ + case UDBE_OK: + return (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB]; + + case UDBE_NO_EEPROM: + default: + return -1; + + case UDBE_INVALID_EEPROM: + return -2; + } +} + + +static struct db_base * +lookup_dbid(int dbid) +{ + if (dbid < 0) + return 0; + + int i; + for (i = 0; all_dboards[i]; i++) + if (all_dboards[i]->dbid == dbid) + return all_dboards[i]; + + return 0; +} + +static struct db_base * +lookup_dboard(int i2c_addr, struct db_base *default_db, char *msg) +{ + struct db_base *db; + int dbid = read_dboard_eeprom(i2c_addr); + + // FIXME removing this printf has the system hang if there are two d'boards + // installed. (I think the problem is in i2c_read/write or the way + // I kludge the zero-byte write to set the read address in eeprom_read.) + printf("%s dbid: 0x%x\n", msg, dbid); + + if (dbid < 0){ // there was some kind of problem. Treat as Basic Tx + return default_db; + } + else if ((db = lookup_dbid(dbid)) == 0){ + printf("No daugherboard code for dbid = 0x%x\n", dbid); + return default_db; + } + return db; +} + +void +set_atr_regs(int bank, struct db_base *db) +{ + uint32_t val[4]; + int shift; + int mask; + int i; + + val[ATR_IDLE] = db->atr_rxval; + val[ATR_RX] = db->atr_rxval; + val[ATR_TX] = db->atr_txval; + val[ATR_FULL] = db->atr_txval; + + if (bank == GPIO_TX_BANK){ + mask = 0xffff0000; + shift = 16; + } + else { + mask = 0x0000ffff; + shift = 0; + } + + for (i = 0; i < 4; i++){ + int t = (atr_regs->v[i] & ~mask) | ((val[i] << shift) & mask); + //printf("atr_regs[%d] = 0x%x\n", i, t); + atr_regs->v[i] = t; + } +} + +static void +set_gpio_mode(int bank, struct db_base *db) +{ + int i; + + hal_gpio_set_ddr(bank, db->output_enables, 0xffff); + set_atr_regs(bank, db); + + for (i = 0; i < 16; i++){ + if (db->used_pins & (1 << i)){ + // set to either GPIO_SEL_SW or GPIO_SEL_ATR + hal_gpio_set_sel(bank, i, (db->atr_mask & (1 << i)) ? 'a' : 's'); + } + } +} + +static int __attribute__((unused)) +determine_tx_mux_value(struct db_base *db) +{ + if (db->i_and_q_swapped) + return 0x01; + else + return 0x10; +} + +static int +determine_rx_mux_value(struct db_base *db) +{ +#define ADC0 0x0 +#define ADC1 0x1 +#define ZERO 0x2 + + static int truth_table[8] = { + /* swap_iq, uses */ + /* 0, 0x0 */ (ZERO << 2) | ZERO, // N/A + /* 0, 0x1 */ (ZERO << 2) | ADC0, + /* 0, 0x2 */ (ZERO << 2) | ADC1, + /* 0, 0x3 */ (ADC1 << 2) | ADC0, + /* 1, 0x0 */ (ZERO << 2) | ZERO, // N/A + /* 1, 0x1 */ (ZERO << 2) | ADC0, + /* 1, 0x2 */ (ZERO << 2) | ADC1, + /* 1, 0x3 */ (ADC0 << 2) | ADC1, + }; + + int subdev0_uses; + int subdev1_uses; + int uses; + + if (db->is_quadrature) + subdev0_uses = 0x3; // uses A/D 0 and 1 + else + subdev0_uses = 0x1; // uses A/D 0 only + + // FIXME second subdev on Basic Rx, LF RX + // if subdev2 exists + // subdev1_uses = 0x2; + subdev1_uses = 0; + + uses = subdev0_uses; + + int swap_iq = db->i_and_q_swapped & 0x1; + int index = (swap_iq << 2) | uses; + + return truth_table[index]; +} + + +void +db_init(void) +{ + int m; + + tx_dboard = lookup_dboard(I2C_ADDR_TX_A, &db_basic_tx, "Tx"); + //printf("db_init: tx dbid = 0x%x\n", tx_dboard->dbid); + set_gpio_mode(GPIO_TX_BANK, tx_dboard); + tx_dboard->init(tx_dboard); + m = determine_tx_mux_value(tx_dboard); + dsp_tx_regs->tx_mux = m; + //printf("tx_mux = 0x%x\n", m); + tx_dboard->current_lo_offset = tx_dboard->default_lo_offset; + + rx_dboard = lookup_dboard(I2C_ADDR_RX_A, &db_basic_rx, "Rx"); + //printf("db_init: rx dbid = 0x%x\n", rx_dboard->dbid); + set_gpio_mode(GPIO_RX_BANK, rx_dboard); + rx_dboard->init(rx_dboard); + m = determine_rx_mux_value(rx_dboard); + dsp_rx_regs->rx_mux = m; + //printf("rx_mux = 0x%x\n", m); + rx_dboard->current_lo_offset = rx_dboard->default_lo_offset; +} + +/*! + * Calculate the frequency to use for setting the digital down converter. + * + * \param[in] target_freq desired RF frequency (Hz) + * \param[in] baseband_freq the RF frequency that corresponds to DC in the IF. + * + * \param[out] dxc_freq is the value for the ddc + * \param[out] inverted is true if we're operating in an inverted Nyquist zone. +*/ +void +calc_dxc_freq(u2_fxpt_freq_t target_freq, u2_fxpt_freq_t baseband_freq, + u2_fxpt_freq_t *dxc_freq, bool *inverted) +{ + u2_fxpt_freq_t fs = U2_DOUBLE_TO_FXPT_FREQ(100e6); // converter sample rate + u2_fxpt_freq_t delta = target_freq - baseband_freq; + +#if 0 + printf("calc_dxc_freq\n"); + printf(" fs = "); print_fxpt_freq(fs); newline(); + printf(" target = "); print_fxpt_freq(target_freq); newline(); + printf(" baseband = "); print_fxpt_freq(baseband_freq); newline(); + printf(" delta = "); print_fxpt_freq(delta); newline(); +#endif + + if (delta >= 0){ + while (delta > fs) + delta -= fs; + if (delta <= fs/2){ // non-inverted region + *dxc_freq = -delta; + *inverted = false; + } + else { // inverted region + *dxc_freq = delta - fs; + *inverted = true; + } + } + else { + while (delta < -fs) + delta += fs; + if (delta >= -fs/2){ // non-inverted region + *dxc_freq = -delta; + *inverted = false; + } + else { // inverted region + *dxc_freq = delta + fs; + *inverted = true; + } + } +} + +bool +db_set_lo_offset(struct db_base *db, u2_fxpt_freq_t offset) +{ + db->current_lo_offset = offset; + return true; +} + +bool +db_tune(struct db_base *db, u2_fxpt_freq_t target_freq, struct tune_result *result) +{ + memset(result, 0, sizeof(*result)); + bool inverted = false; + u2_fxpt_freq_t dxc_freq; + u2_fxpt_freq_t actual_dxc_freq; + + // Ask the d'board to tune as closely as it can to target_freq+lo_offset + bool ok = db->set_freq(db, target_freq+db->current_lo_offset, &result->baseband_freq); + + // Calculate the DDC setting that will downconvert the baseband from the + // daughterboard to our target frequency. + calc_dxc_freq(target_freq, result->baseband_freq, &dxc_freq, &inverted); + + // If the spectrum is inverted, and the daughterboard doesn't do + // quadrature downconversion, we can fix the inversion by flipping the + // sign of the dxc_freq... (This only happens using the basic_rx board) + + if (db->spectrum_inverted) + inverted = !inverted; + + if (inverted && !db->is_quadrature){ + dxc_freq = -dxc_freq; + inverted = !inverted; + } + + if (db->is_tx){ + dxc_freq = -dxc_freq; // down conversion versus up conversion + ok &= db_set_duc_freq(dxc_freq, &actual_dxc_freq); + } + else { + ok &= db_set_ddc_freq(dxc_freq, &actual_dxc_freq); + } + + result->dxc_freq = dxc_freq; + result->residual_freq = dxc_freq - actual_dxc_freq; + result->inverted = inverted; + return ok; +} + +static int32_t +compute_freq_control_word(u2_fxpt_freq_t target_freq, u2_fxpt_freq_t *actual_freq) +{ + // If we were using floating point, we'd calculate + // master = 100e6; + // v = (int) rint(target_freq / master_freq) * pow(2.0, 32.0); + + //printf("compute_freq_control_word\n"); + //printf(" target_freq = "); print_fxpt_freq(target_freq); newline(); + + int32_t master_freq = 100000000; // 100M + + int32_t v = ((target_freq << 12)) / master_freq; + //printf(" fcw = %d\n", v); + + *actual_freq = (v * (int64_t) master_freq) >> 12; + + //printf(" actual = "); print_fxpt_freq(*actual_freq); newline(); + + return v; +} + + +bool +db_set_ddc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq) +{ + int32_t v = compute_freq_control_word(dxc_freq, actual_dxc_freq); + dsp_rx_regs->freq = v; + return true; +} + +bool +db_set_duc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq) +{ + int32_t v = compute_freq_control_word(dxc_freq, actual_dxc_freq); + dsp_tx_regs->freq = v; + return true; +} + +bool +db_set_gain(struct db_base *db, u2_fxpt_gain_t gain) +{ + return db->set_gain(db, gain); +} diff --git a/usrp2/firmware/lib/db_wbxng.c b/usrp2/firmware/lib/db_wbxng.c new file mode 100644 index 000000000..c02a5bdaa --- /dev/null +++ b/usrp2/firmware/lib/db_wbxng.c @@ -0,0 +1,214 @@ +/* + * Copyright 2010 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + + +#include "db_wbxng.h" +#include "adf4350.h" +#include <spi.h> +#include <memory_map.h> +#include <db_base.h> +#include <hal_io.h> +#include <mdelay.h> +#include <lsdac.h> +#include <clocks.h> +#include <stdio.h> +#include <stdint.h> + +bool wbxng_init_rx(struct db_base *dbb); +bool wbxng_init_tx(struct db_base *dbb); +bool wbxng_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc); +bool wbxng_set_gain_rx(struct db_base *dbb, u2_fxpt_gain_t gain); +bool wbxng_set_gain_tx(struct db_base *dbb, u2_fxpt_gain_t gain); +bool wbxng_set_tx_enable(struct db_base *dbb, bool on); + + +/* + * The class instances + */ +struct db_wbxng_rx db_wbxng_rx = { + .base.dbid = 0x0053, + .base.is_tx = false, + .base.output_enables = RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5|PLL_CE|PLL_PDBRF|ATTN_MASK, + .base.used_pins = 0xFFFF, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(67.5e6), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2200e6), + .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(31.5), + .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.5), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0), + .base.init = wbxng_init_rx, + .base.set_freq = wbxng_set_freq, + .base.set_gain = wbxng_set_gain_rx, + .base.set_tx_enable = 0, + .base.atr_mask = RXBB_EN | RX2_RX1N, + .base.atr_txval = RX2_RX1N, + .base.atr_rxval = RXBB_EN, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.adf4350_regs_int = UINT16_C(100), + .common.adf4350_regs_frac = 0, + .common.adf4350_regs_prescaler = 1, + .common.adf4350_regs_mod = UINT16_C(0xfff), + .common.adf4350_regs_10_bit_r_counter = UINT16_C(1), + .common.adf4350_regs_divider_select = 0, + .common.adf4350_regs_8_bit_band_select_clock_divider_value = 0, + .common.spi_mask = SPI_SS_RX_DB, + .common.freq_mult = 2 +}; + + +struct db_wbxng_tx db_wbxng_tx = { + .base.dbid = 0x0052, + .base.is_tx = true, + .base.output_enables = RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5|PLL_CE|PLL_PDBRF, + .base.used_pins = 0xFFFF, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(67.5e6), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2200e6), + .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(25), + .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.1), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0), + .base.init = wbxng_init_tx, + .base.set_freq = wbxng_set_freq, + .base.set_gain = wbxng_set_gain_tx, + .base.set_tx_enable = wbxng_set_tx_enable, + .base.atr_mask = RX_TXN | TXMOD_EN, + .base.atr_txval = TXMOD_EN, + .base.atr_rxval = RX_TXN, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.adf4350_regs_int = UINT16_C(100), + .common.adf4350_regs_frac = 0, + .common.adf4350_regs_prescaler = 1, + .common.adf4350_regs_mod = UINT16_C(0xfff), + .common.adf4350_regs_10_bit_r_counter = UINT16_C(1), + .common.adf4350_regs_divider_select = 0, + .common.adf4350_regs_8_bit_band_select_clock_divider_value = 0, + .common.spi_mask = SPI_SS_TX_DB, + .common.freq_mult = 2 +}; + + +bool +wbxng_init_tx(struct db_base *dbb) +{ + //struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + clocks_enable_tx_dboard(true, 0); + hal_gpio_write( GPIO_TX_BANK, ENABLE_5|ENABLE_33, ENABLE_5|ENABLE_33 ); + + adf4350_init(dbb); + + // Set the freq now to get the one time 10ms delay out of the way. + u2_fxpt_freq_t dc; + dbb->set_freq(dbb, dbb->freq_min, &dc); + return true; +} + +bool +wbxng_init_rx(struct db_base *dbb) +{ + //struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + clocks_enable_rx_dboard(true, 0); + hal_gpio_write( GPIO_RX_BANK, ENABLE_5|ENABLE_33, ENABLE_5|ENABLE_33 ); + + adf4350_init(dbb); + + // test gain + dbb->set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(20.0)); + + // Set the freq now to get the one time 10ms delay out of the way. + u2_fxpt_freq_t dc; + dbb->set_freq(dbb, dbb->freq_min, &dc); + + return true; +} + +bool +wbxng_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc) +{ + bool ok = adf4350_set_freq(2*freq,dbb); + *dc = adf4350_get_freq(dbb)/2; + + return ok; +} + +bool +wbxng_set_gain_tx(struct db_base *dbb, u2_fxpt_gain_t gain) +{ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + // clamp gain + //gain = max(db->gain_min, min(gain, db->gain_max)); + + int offset_q8 = (int)(1.4/3.3*4096*(1<<15)); + int range_q15 = (int)(-0.9*4096/3.3*256*128); + int slope_q8 = range_q15/db->base.gain_max; + + int dacword = ((slope_q8 * gain) + offset_q8)>>15; + //printf("DACWORD 0x%x\n",dacword); + lsdac_write_tx(0,dacword); + return true; +} + +bool +wbxng_set_gain_rx(struct db_base *dbb, u2_fxpt_gain_t gain) +{ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + // clamp gain + //gain = max(db->gain_min, min(gain, db->gain_max)); + + int iobits = (int) ((~((db->base.gain_max - gain) << 2)) & ATTN_MASK); + //printf("gain %d, gainmax %d, RX_ATTN_MASK = 0x%x, RX_ATTN_WORD = 0x%x\n", gain, db->base.gain_max, (int) (ATTN_MASK), (int) (iobits)); + + hal_gpio_write( GPIO_RX_BANK, (int) (iobits), ATTN_MASK ); + return true; +} + + +bool +wbxng_set_tx_enable(struct db_base *dbb, bool on) +{ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + // FIXME + + return false; +} + +bool +wbxng_lock_detect(struct db_base *dbb) +{ + struct db_wbxng_dummy *db = (struct db_wbxng_dummy *) dbb; + + int pins; + pins = hal_gpio_read( db->base.is_tx ? GPIO_TX_BANK : GPIO_RX_BANK ); + if(pins & PLL_LOCK_DETECT) + //printf("Got Locked Status from Synth"); + return true; + + //printf("Got Unlocked Status from Synth"); + return false; +} + diff --git a/usrp2/firmware/lib/db_wbxng.h b/usrp2/firmware/lib/db_wbxng.h new file mode 100644 index 000000000..3756e6c24 --- /dev/null +++ b/usrp2/firmware/lib/db_wbxng.h @@ -0,0 +1,74 @@ +/* + * Copyright 2010 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef DB_WBXNG_H +#define DB_WBXNG_H + +#include <db_base.h> + +// IO Pin functions +// Tx and Rx have shared defs, but different i/o regs +#define ENABLE_5 (1 << 7) // enables 5.0V power supply +#define ENABLE_33 (1 << 6) // enables 3.3V supply +//#define RX_TXN (1 << 15) // Tx only: T/R antenna switch for TX/RX port +//#define RX2_RX1N (1 << 15) // Rx only: antenna switch between RX2 and TX/RX port +#define RX_TXN ((1 << 5)|(1 << 15)) // Tx only: T/R antenna switch for TX/RX port +#define RX2_RX1N ((1 << 5)|(1 << 15)) // Rx only: antenna switch between RX2 and TX/RX port +#define RXBB_EN (1 << 4) +#define TXMOD_EN (1 << 4) +#define PLL_CE (1 << 3) +#define PLL_PDBRF (1 << 2) +#define PLL_MUXOUT (1 << 1) +#define PLL_LOCK_DETECT (1 << 0) + +// RX Attenuator constants +#define ATTN_SHIFT 8 +#define ATTN_MASK (63 << ATTN_SHIFT) + +struct db_wbxng_common { + // RFX common stuff + uint16_t adf4350_regs_int; + uint16_t adf4350_regs_frac; + uint8_t adf4350_regs_prescaler; + uint16_t adf4350_regs_mod; + uint16_t adf4350_regs_10_bit_r_counter; + uint8_t adf4350_regs_divider_select; + uint8_t adf4350_regs_8_bit_band_select_clock_divider_value; + + int freq_mult; + int spi_mask; +}; + +struct db_wbxng_dummy { + struct db_base base; + struct db_wbxng_common common; +}; + + +struct db_wbxng_rx { + struct db_base base; + struct db_wbxng_common common; +}; + +struct db_wbxng_tx { + struct db_base base; + struct db_wbxng_common common; +}; + + +#endif /* DB_WBXNG_H */ |