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-rw-r--r--usrp2/firmware/lib/Makefile.am76
-rw-r--r--usrp2/firmware/lib/adf4350.c4
-rw-r--r--usrp2/firmware/lib/db.h5
-rw-r--r--usrp2/firmware/lib/db_base.h1
-rw-r--r--usrp2/firmware/lib/db_basic.c4
-rw-r--r--usrp2/firmware/lib/db_bitshark_rx.c337
-rw-r--r--usrp2/firmware/lib/db_bitshark_rx.h46
-rw-r--r--usrp2/firmware/lib/db_dbsrx.c1
-rw-r--r--usrp2/firmware/lib/db_init.c14
-rw-r--r--usrp2/firmware/lib/db_init_wbx.c7
-rw-r--r--usrp2/firmware/lib/db_init_xcvr.c404
-rw-r--r--usrp2/firmware/lib/db_rfx.c10
-rw-r--r--usrp2/firmware/lib/db_tvrx.c3
-rw-r--r--usrp2/firmware/lib/db_wbxng.c16
-rw-r--r--usrp2/firmware/lib/db_xcvr2450.c25
15 files changed, 893 insertions, 60 deletions
diff --git a/usrp2/firmware/lib/Makefile.am b/usrp2/firmware/lib/Makefile.am
index 8b7762d40..d6bb4edc3 100644
--- a/usrp2/firmware/lib/Makefile.am
+++ b/usrp2/firmware/lib/Makefile.am
@@ -19,29 +19,22 @@ include $(top_srcdir)/Makefile.common
noinst_LIBRARIES = \
libu2fw.a \
- libu2fw_wbx.a
+ libu2fw_wbx.a \
+ libu2fw_xcvr.a
-
-libu2fw_a_SOURCES = \
+U2FW_COMMON = \
+ _exit.c \
abort.c \
ad9510.c \
- adf4350.c \
- adf4350_regs.c \
ad9777.c \
bsm12.c \
buffer_pool.c \
clocks.c \
db_basic.c \
- db_dbsrx.c \
- db_rfx.c \
- db_tvrx.c \
- db_xcvr2450.c \
- db_init.c \
dbsm.c \
eeprom.c \
- ethernet.c \
eth_mac.c \
- _exit.c \
+ ethernet.c \
exit.c \
hal_io.c \
hal_uart.c \
@@ -53,51 +46,37 @@ libu2fw_a_SOURCES = \
memset_wa.c \
nonstdio.c \
pic.c \
+ print_buffer.c \
+ print_fxpt.c \
print_mac_addr.c \
print_rmon_regs.c \
- print_fxpt.c \
- print_buffer.c \
printf.c \
sd.c \
spi.c \
- u2_init.c
+ u2_init.c
+
+libu2fw_a_SOURCES = \
+ $(U2FW_COMMON) \
+ db_init.c \
+ db_bitshark_rx.c \
+ db_dbsrx.c \
+ db_rfx.c \
+ db_tvrx.c
libu2fw_wbx_a_SOURCES = \
- abort.c \
- ad9510.c \
+ $(U2FW_COMMON) \
+ db_init_wbx.c \
adf4350.c \
adf4350_regs.c \
- ad9777.c \
- bsm12.c \
- buffer_pool.c \
- clocks.c \
- db_basic.c \
- db_wbxng.c \
- db_init_wbx.c \
- dbsm.c \
- eeprom.c \
- ethernet.c \
- eth_mac.c \
- _exit.c \
- exit.c \
- hal_io.c \
- hal_uart.c \
- i2c.c \
- lsadc.c \
- lsdac.c \
- mdelay.c \
- memcpy_wa.c \
- memset_wa.c \
- nonstdio.c \
- pic.c \
- print_mac_addr.c \
- print_rmon_regs.c \
- print_fxpt.c \
- print_buffer.c \
- printf.c \
- sd.c \
- spi.c \
- u2_init.c
+ db_wbxng.c
+
+libu2fw_xcvr_a_SOURCES = \
+ $(U2FW_COMMON) \
+ db_init_xcvr.c \
+ adf4350.c \
+ adf4350_regs.c \
+ db_xcvr2450.c
+
noinst_HEADERS = \
ad9510.h \
@@ -112,6 +91,7 @@ noinst_HEADERS = \
db.h \
db_base.h \
db_wbxng.h \
+ db_bitshark_rx.h \
dbsm.h \
eth_mac.h \
eth_mac_regs.h \
diff --git a/usrp2/firmware/lib/adf4350.c b/usrp2/firmware/lib/adf4350.c
index 0725c9337..dbab654ea 100644
--- a/usrp2/firmware/lib/adf4350.c
+++ b/usrp2/firmware/lib/adf4350.c
@@ -30,7 +30,7 @@
#define MIN_VCO_FREQ U2_DOUBLE_TO_FXPT_FREQ(2.2e9) /* minimum vco freq */
#define MAX_VCO_FREQ U2_DOUBLE_TO_FXPT_FREQ(4.4e9) /* minimum vco freq */
#define MAX_FREQ MAX_VCO_FREQ /* upper bound freq (rf div = 1) */
-#define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV) /* calculated lower bound freq */
+#define MIN_FREQ U2_DOUBLE_TO_FXPT_FREQ(68.75e6) /* lower bound freq (rf div = 16) */
u2_fxpt_freq_t adf4350_get_max_freq(void){
return MAX_FREQ;
@@ -170,7 +170,7 @@ bool adf4350_set_freq(u2_fxpt_freq_t freq, struct db_base *dbb){
adf4350_load_register(2, dbb);
adf4350_load_register(4, dbb);
adf4350_load_register(0, dbb); /* register 0 must be last */
- return true;
+ return adf4350_get_locked(dbb);
}
u2_fxpt_freq_t adf4350_get_freq(struct db_base *dbb){
diff --git a/usrp2/firmware/lib/db.h b/usrp2/firmware/lib/db.h
index 7feb1c889..9c0f41da5 100644
--- a/usrp2/firmware/lib/db.h
+++ b/usrp2/firmware/lib/db.h
@@ -99,7 +99,10 @@ db_set_duc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq);
*/
bool
db_set_gain(struct db_base *db, u2_fxpt_gain_t gain);
-
+
+bool
+db_set_antenna(struct db_base *db, int ant);
+
/*!
* \brief Read the eeprom value from the db, without defaulting to BasicRX/TX
*/
diff --git a/usrp2/firmware/lib/db_base.h b/usrp2/firmware/lib/db_base.h
index 2ccfbf509..1945efe0b 100644
--- a/usrp2/firmware/lib/db_base.h
+++ b/usrp2/firmware/lib/db_base.h
@@ -63,6 +63,7 @@ struct db_base {
bool (*set_freq)(struct db_base *, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
bool (*set_gain)(struct db_base *, u2_fxpt_gain_t gain);
bool (*set_tx_enable)(struct db_base *, bool on);
+ bool (*set_antenna)(struct db_base *, int ant);
};
diff --git a/usrp2/firmware/lib/db_basic.c b/usrp2/firmware/lib/db_basic.c
index 2bd4ebfbe..8f86f060b 100644
--- a/usrp2/firmware/lib/db_basic.c
+++ b/usrp2/firmware/lib/db_basic.c
@@ -53,6 +53,7 @@ struct db_basic db_basic_tx = {
.base.set_freq = db_basic_set_freq,
.base.set_gain = db_basic_set_gain,
.base.set_tx_enable = db_basic_set_tx_enable,
+ .base.set_antenna = 0,
};
struct db_basic db_basic_rx = {
@@ -79,6 +80,7 @@ struct db_basic db_basic_rx = {
.base.set_freq = db_basic_set_freq,
.base.set_gain = db_basic_set_gain,
.base.set_tx_enable = db_basic_set_tx_enable,
+ .base.set_antenna = 0,
};
struct db_basic db_lf_tx = {
@@ -105,6 +107,7 @@ struct db_basic db_lf_tx = {
.base.set_freq = db_basic_set_freq,
.base.set_gain = db_basic_set_gain,
.base.set_tx_enable = db_basic_set_tx_enable,
+ .base.set_antenna = 0,
};
struct db_basic db_lf_rx = {
@@ -131,6 +134,7 @@ struct db_basic db_lf_rx = {
.base.set_freq = db_basic_set_freq,
.base.set_gain = db_basic_set_gain,
.base.set_tx_enable = db_basic_set_tx_enable,
+ .base.set_antenna = 0,
};
diff --git a/usrp2/firmware/lib/db_bitshark_rx.c b/usrp2/firmware/lib/db_bitshark_rx.c
new file mode 100644
index 000000000..4c126de9b
--- /dev/null
+++ b/usrp2/firmware/lib/db_bitshark_rx.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright 2010 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "db_bitshark_rx.h"
+#include <memory_map.h>
+#include <db_base.h>
+#include <hal_io.h>
+#include <mdelay.h>
+#include <lsdac.h>
+#include <clocks.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <i2c.h>
+
+/* Note: Thie general structure of this file is based on the db_wbxng.c
+ codebase for the wbx daughterboard. */
+
+/* The following defines specify the address map provided by the
+ Bitshark USRP Rx (BURX) board. These registers are all accessed over I2C. */
+#define RF_CENTER_FREQ_REG 0x00
+#define RF_CHAN_FILTER_BW_REG 0x01
+#define RF_GAIN_REG 0x02
+#define BB_GAIN_REG 0x03
+#define ADF4350_REG 0x10
+#define SKY73202_REG 0x11
+#define CLOCK_SCHEME_REG 0x20
+
+/* The following table lists the registers provided by the Bitshark board
+ that are accessible over I2C:
+ --------------------------------------------------------
+ |RegAddr: 0x00-RF Center Freq register |
+ |4-bytes 0x00|
+ |4-byte unsigned RF center freq (in KHz)|
+ |RegAddr: 0x01-RF channel filter bandwidth register |
+ |4-bytes 0x00|
+ |4-byte unsigned RF channel filter bw (in KHz)|
+ |RegAddr: 0x02-RF gain register |
+ |7-bytes 0x00|
+ |1-byte signed RF gain (in dB)|
+ |RegAddr: 0x03-Baseband gain register |
+ |4-bytes 0x00|
+ |4-byte signed baseband filter gain (in dB)|
+ |RegAddr: 0x10-ADF4350 register |
+ |4-bytes 0x00|
+ |4-byte ADF4350 register value (actual ADF4350 reg addr embedded
+ within 4-byte value)|
+ |RegAddr: 0x11-SKY73202 register |
+ |5-bytes 0x00|
+ |1-byte reg 0 of SKY73202 |
+ |1-byte reg 1 of SKY73202 |
+ |1-byte reg 2 of SKY73202 |
+ |RegAddr: 0x20-Clock Scheme |
+ |3-bytes 0x00|
+ |1-byte indicating clocking scheme:
+ -0x00 -> BURX local TCXO off, BURX accepts ref clock from
+ USRP2 (freq of USRP2's ref clock specified in bytes 2-5)
+ -0x01 -> BURX local TCXO on, BURX uses its local TCXO as its ref
+ clock, TCXO signal output for use as phase lock for USRP2 |
+ |4-byte USRP2 ref clock freq in hz (only needed if byte 1 set to 0x00) |
+
+ ---------------------------------------------------------------------------
+
+ As an example, lets say the client wants to set an RF center freq of
+ 1000 MHz. In KHz, this translates to 1000000 (resolution is only down to
+ steps of 1 KHz), which is 0x000F4240 in hex. So the complete 9-byte I2C
+ sequence that the client should send is as follows:
+ byte 0: 0x00-register 0x00 is the target of the write operation
+ bytes 1-4: 0x00 (padding)
+ byte 5: 0x00 (MSB of the 1000000 KHz value, in hex)
+ byte 6: 0x0F
+ byte 7: 0x42
+ byte 8: 0x40 (LSB of the 1000000 KHz value, in hex)
+
+ How about another example...lets say the client wants to setup the clock
+ scheme to use scheme #1 where the 26 MHz TCXO on the BURX board is enabled,
+ and is provided to the USRP2 for it to phase lock to it as an external ref.
+ 26 MHz (i.e. 26 million), in hex, is 0x18CBA80.
+ So the complete 9-byte I2C sequence that the client should send is as follows:
+ byte 0: 0x20-register 0x20 is the target of the write operation
+ bytes 1-3: 0x00 (padding)
+ byte 4: 0x01 (indicating that clock scheme #1 is wanted)
+ byte 5: 0x01 (MSB of the BURX ref clk freq)
+ byte 6: 0x8C
+ byte 7: 0xBA
+ byte 8: 0x80 (LSB of the BURX ref clk freq)
+
+ Note: The endian-ness of 4-byte values used in I2C cmds is different on
+ USRP2 compared to USRP1.
+
+*/
+
+#define NUM_BYTES_IN_I2C_CMD 9
+#define I2C_ADDR 0x47
+
+bool bitshark_rx_init(struct db_base *dbb);
+bool bitshark_rx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
+bool bitshark_rx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain);
+bool bitshark_rx_set_bw(struct db_base *dbb, uint16_t bw);
+
+static bool set_clock_scheme(uint8_t clock_scheme, uint32_t ref_clk_freq);
+
+/*
+ * The class instances
+ */
+struct db_bitshark_rx db_bitshark_rx = {
+ .base.dbid = 0x0070,
+ .base.is_tx = false,
+ .base.output_enables = 0x0000,
+ .base.used_pins = 0x0000,
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(300e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(4000e6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(42),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(6),
+ .base.is_quadrature = true,
+ .base.i_and_q_swapped = true,
+ .base.spectrum_inverted = false,
+ .base.default_lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
+ .base.init = bitshark_rx_init,
+ .base.set_freq = bitshark_rx_set_freq,
+ .base.set_gain = bitshark_rx_set_gain,
+ .base.set_tx_enable = 0,
+ .base.atr_mask = 0x0000,
+ .base.atr_txval = 0,
+ .base.atr_rxval = 0,
+ .base.set_antenna = 0,
+ .extra.bw_min = 660, /* in KHz, so 660 KHz */
+ .extra.bw_max = 56000, /* in KHz, so 56 MHz */
+ .extra.set_bw = bitshark_rx_set_bw
+};
+
+bool
+bitshark_rx_init(struct db_base *dbb)
+{
+ struct db_bitshark_rx_dummy *db = (struct db_bitshark_rx_dummy *) dbb;
+
+ clocks_enable_rx_dboard(true, 0);
+ /* hal_gpio_write( GPIO_RX_BANK, ENABLE_5|ENABLE_33, ENABLE_5|ENABLE_33 ); */
+ /* above isn't needed, since we don't have any GPIO from the FPGA */
+
+ /* setup the clock scheme to accept the USRP2's 100 MHz ref clk */
+ set_clock_scheme(0,100000000);
+
+ /* initial setting of gain */
+ dbb->set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(20.0));
+
+ /* Set the freq now to get the one time 10ms delay out of the way. */
+ u2_fxpt_freq_t dc;
+ dbb->set_freq(dbb, dbb->freq_min, &dc);
+
+ /* set up the RF bandwidth of the signal of interest...Note: there
+ doesn't appear to be a standard way of setting this bandwidth
+ in USRP2-land (compared to USRP1-land, where we have the
+ straight-forward set_bw() method). Not sure why this is, but
+ for now, simply set the bandwidth once for the intended
+ application. */
+ db->extra.set_bw(dbb, 25000); /* 25 MHz channel bw */
+
+ return true;
+}
+
+bool
+bitshark_rx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc)
+{
+ struct db_bitshark_rx_dummy *db = (struct db_bitshark_rx_dummy *) dbb;
+ unsigned char args[NUM_BYTES_IN_I2C_CMD];
+ unsigned char val[4];
+ uint32_t freq_in_khz = (uint32_t)(u2_fxpt_freq_round_to_uint(freq)/1000);
+
+ if(!(freq>=db->base.freq_min && freq<=db->base.freq_max))
+ {
+ return false;
+ }
+
+ memset(args,0x00,NUM_BYTES_IN_I2C_CMD);
+ memcpy(val,&freq_in_khz,4);
+ args[0] = RF_CENTER_FREQ_REG;
+ args[5] = val[3];
+ args[6] = val[2];
+ args[7] = val[1];
+ args[8] = val[0];
+
+ i2c_write(I2C_ADDR, args, NUM_BYTES_IN_I2C_CMD);
+ /* Add a brief delay after each command. This only seems to be
+ necessary when sending a sequence of commands one after the other.
+ This issue appears to be specific to the USRP2, since it isn't
+ necessary on the USRP1. The 5 mS delay is a bit of
+ an emperical compromise: too short (say, 1 mS), and every once
+ in a great while a command will still be magically dropped on its
+ way out...too long (say, 500 mS) and higher-level apps such as
+ usrp2_fft.py seem to choke because the init sequence is taking
+ too long. So 5 mS was tested repeatedly without error, and deemed
+ reasonable. Not sure if this is an issue with the I2C master
+ code in the microblaze or some place else, and I hate magic
+ delays too, but this seems to be stable. */
+ mdelay(5);
+
+ *dc = freq;
+ return true;
+}
+
+bool
+bitshark_rx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain)
+{
+ struct db_bitshark_rx_dummy *db = (struct db_bitshark_rx_dummy *) dbb;
+
+ unsigned char args[NUM_BYTES_IN_I2C_CMD];
+ uint8_t final_gain = (uint8_t)(u2_fxpt_gain_round_to_int(gain));
+
+ if(!(gain >= db->base.gain_min && gain <= db->base.gain_max))
+ {
+ return false;
+ }
+
+ memset(args,0x00,NUM_BYTES_IN_I2C_CMD);
+ args[0] = RF_GAIN_REG;
+ args[5] = final_gain;
+
+ i2c_write(I2C_ADDR, args, NUM_BYTES_IN_I2C_CMD);
+ /* Add a brief delay after each command. This only seems to be
+ necessary when sending a sequence of commands one after the other.
+ This issue appears to be specific to the USRP2, since it isn't
+ necessary on the USRP1. The 5 mS delay is a bit of
+ an emperical compromise: too short (say, 1 mS), and every once
+ in a great while a command will still be magically dropped on its
+ way out...too long (say, 500 mS) and higher-level apps such as
+ usrp2_fft.py seem to choke because the init sequence is taking
+ too long. So 5 mS was tested repeatedly without error, and deemed
+ reasonable. Not sure if this is an issue with the I2C master
+ code in the microblaze or some place else, and I hate magic
+ delays too, but this seems to be stable. */
+ mdelay(5);
+
+ return true;
+}
+
+bool
+bitshark_rx_set_bw(struct db_base *dbb, uint16_t bw_in_khz)
+{
+ struct db_bitshark_rx_dummy *db = (struct db_bitshark_rx_dummy *) dbb;
+ unsigned char val[2];
+ unsigned char args[NUM_BYTES_IN_I2C_CMD];
+
+ if(!(bw_in_khz >= db->extra.bw_min && bw_in_khz <= db->extra.bw_max))
+ {
+ return false;
+ }
+
+ memset(args,0x00,NUM_BYTES_IN_I2C_CMD);
+ memcpy(val,&bw_in_khz,2);
+ args[0] = RF_CHAN_FILTER_BW_REG;
+ args[5] = val[1];
+ args[6] = val[0];
+
+ i2c_write(I2C_ADDR, args, NUM_BYTES_IN_I2C_CMD);
+ /* Add a brief delay after each command. This only seems to be
+ necessary when sending a sequence of commands one after the other.
+ This issue appears to be specific to the USRP2, since it isn't
+ necessary on the USRP1. The 5 mS delay is a bit of
+ an emperical compromise: too short (say, 1 mS), and every once
+ in a great while a command will still be magically dropped on its
+ way out...too long (say, 500 mS) and higher-level apps such as
+ usrp2_fft.py seem to choke because the init sequence is taking
+ too long. So 5 mS was tested repeatedly without error, and deemed
+ reasonable. Not sure if this is an issue with the I2C master
+ code in the microblaze or some place else, and I hate magic
+ delays too, but this seems to be stable. */
+ mdelay(5);
+
+ return true;
+}
+
+static bool
+set_clock_scheme(uint8_t clock_scheme, uint32_t ref_clk_freq)
+{
+ /* Set the clock scheme for determining how the BURX
+ dboard receives its clock. For the USRP2, there is really only
+ one way of doing this, which is to use the 100 MHz ref clk
+ on the USRP2 as its reference. However, it is possible to
+ use the BURX's 26 MHz TCXO as the external reference input to
+ the USRP, which would provide phase lock between our oscillator
+ and the USRP's 100 MHz oscillator. And since the BURX board
+ provides the ability to warp the oscillator, this may be
+ useful to some folks. Otherwise, the BURX board will always
+ just take the 100 MHz reference from the USRP2 as its reference.
+ */
+
+ unsigned char args[NUM_BYTES_IN_I2C_CMD];
+ char val[4];
+
+ if (clock_scheme > 1)
+ {
+ return false;
+ }
+
+ memcpy(val,&ref_clk_freq,4);
+ args[0] = CLOCK_SCHEME_REG;
+ args[4] = clock_scheme;
+ args[5] = val[3];
+ args[6] = val[2];
+ args[7] = val[1];
+ args[8] = val[0];
+
+ i2c_write(I2C_ADDR, args, NUM_BYTES_IN_I2C_CMD);
+ /* Add a brief delay after each command. This only seems to be
+ necessary when sending a sequence of commands one after the other.
+ This issue appears to be specific to the USRP2, since it isn't
+ necessary on the USRP1. The 5 mS delay is a bit of
+ an emperical compromise: too short (say, 1 mS), and every once
+ in a great while a command will still be magically dropped on its
+ way out...too long (say, 500 mS) and higher-level apps such as
+ usrp2_fft.py seem to choke because the init sequence is taking
+ too long. So 5 mS was tested repeatedly without error, and deemed
+ reasonable. Not sure if this is an issue with the I2C master
+ code in the microblaze or some place else, and I hate magic
+ delays too, but this seems to be stable. */
+ mdelay(5);
+
+ return true;
+}
+
diff --git a/usrp2/firmware/lib/db_bitshark_rx.h b/usrp2/firmware/lib/db_bitshark_rx.h
new file mode 100644
index 000000000..3651f27b8
--- /dev/null
+++ b/usrp2/firmware/lib/db_bitshark_rx.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2010 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef DB_BITSHARK_RX_H
+#define DB_BITSHARK_RX_H
+
+#include <db_base.h>
+
+struct db_bitshark_rx_extra
+{
+ uint16_t bw_min;
+ uint16_t bw_max;
+ bool (*set_bw)(struct db_base *, uint16_t bw);
+
+};
+
+struct db_bitshark_rx_dummy
+{
+ struct db_base base;
+ struct db_bitshark_rx_extra extra;
+};
+
+
+struct db_bitshark_rx
+{
+ struct db_base base;
+ struct db_bitshark_rx_extra extra;
+};
+
+
+#endif /* DB_BITSHARK_RX_H */
diff --git a/usrp2/firmware/lib/db_dbsrx.c b/usrp2/firmware/lib/db_dbsrx.c
index 2174a6cd8..ce1300bf2 100644
--- a/usrp2/firmware/lib/db_dbsrx.c
+++ b/usrp2/firmware/lib/db_dbsrx.c
@@ -103,6 +103,7 @@ struct db_dbsrx db_dbsrx = {
.common.d_adl = 0,
.common.d_gc2 = 31,
.common.d_diag = 0,
+ .base.set_antenna = 0,
};
bool
diff --git a/usrp2/firmware/lib/db_init.c b/usrp2/firmware/lib/db_init.c
index 5104f3ce0..d58badc9e 100644
--- a/usrp2/firmware/lib/db_init.c
+++ b/usrp2/firmware/lib/db_init.c
@@ -51,9 +51,7 @@ extern struct db_base db_tvrx1;
extern struct db_base db_tvrx2;
extern struct db_base db_tvrx3;
extern struct db_base db_dbsrx;
-
-extern struct db_base db_xcvr2450_tx;
-extern struct db_base db_xcvr2450_rx;
+extern struct db_base db_bitshark_rx;
struct db_base *all_dboards[] = {
&db_basic_tx,
@@ -76,8 +74,7 @@ struct db_base *all_dboards[] = {
#endif
&db_tvrx3,
&db_dbsrx,
- &db_xcvr2450_tx,
- &db_xcvr2450_rx,
+ &db_bitshark_rx,
0
};
@@ -428,3 +425,10 @@ db_set_gain(struct db_base *db, u2_fxpt_gain_t gain)
{
return db->set_gain(db, gain);
}
+
+bool
+db_set_antenna(struct db_base *db, int ant)
+{
+ if (db->set_antenna == 0) return false;
+ return db->set_antenna(db, ant);
+}
diff --git a/usrp2/firmware/lib/db_init_wbx.c b/usrp2/firmware/lib/db_init_wbx.c
index d7fa20cf9..8810e0d4d 100644
--- a/usrp2/firmware/lib/db_init_wbx.c
+++ b/usrp2/firmware/lib/db_init_wbx.c
@@ -395,3 +395,10 @@ db_set_gain(struct db_base *db, u2_fxpt_gain_t gain)
{
return db->set_gain(db, gain);
}
+
+bool
+db_set_antenna(struct db_base *db, int ant)
+{
+ if (db->set_antenna == 0) return false;
+ return db->set_antenna(db, ant);
+}
diff --git a/usrp2/firmware/lib/db_init_xcvr.c b/usrp2/firmware/lib/db_init_xcvr.c
new file mode 100644
index 000000000..3e3d3eb86
--- /dev/null
+++ b/usrp2/firmware/lib/db_init_xcvr.c
@@ -0,0 +1,404 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008,2009 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include <memory_map.h>
+#include <i2c.h>
+#include <usrp2_i2c_addr.h>
+#include <string.h>
+#include <stdio.h>
+#include <db.h>
+#include <db_base.h>
+#include <hal_io.h>
+#include <nonstdio.h>
+
+
+struct db_base *tx_dboard; // the tx daughterboard that's installed
+struct db_base *rx_dboard; // the rx daughterboard that's installed
+
+extern struct db_base db_basic_tx;
+extern struct db_base db_basic_rx;
+extern struct db_base db_lf_tx;
+extern struct db_base db_lf_rx;
+extern struct db_base db_xcvr2450_tx;
+extern struct db_base db_xcvr2450_rx;
+
+struct db_base *all_dboards[] = {
+ &db_basic_tx,
+ &db_basic_rx,
+ &db_lf_tx,
+ &db_lf_rx,
+ &db_xcvr2450_rx,
+ &db_xcvr2450_tx,
+ 0
+};
+
+
+typedef enum { UDBE_OK, UDBE_NO_EEPROM, UDBE_INVALID_EEPROM } usrp_dbeeprom_status_t;
+
+static usrp_dbeeprom_status_t
+read_raw_dboard_eeprom (unsigned char *buf, int i2c_addr)
+{
+ if (!eeprom_read (i2c_addr, 0, buf, DB_EEPROM_CLEN))
+ return UDBE_NO_EEPROM;
+
+ if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
+ return UDBE_INVALID_EEPROM;
+
+ int sum = 0;
+ unsigned int i;
+ for (i = 0; i < DB_EEPROM_CLEN; i++)
+ sum += buf[i];
+
+ if ((sum & 0xff) != 0)
+ return UDBE_INVALID_EEPROM;
+
+ return UDBE_OK;
+}
+
+
+/*
+ * Return DBID, -1 <none> or -2 <invalid eeprom contents>
+ */
+int
+read_dboard_eeprom(int i2c_addr)
+{
+ unsigned char buf[DB_EEPROM_CLEN];
+
+ usrp_dbeeprom_status_t s = read_raw_dboard_eeprom (buf, i2c_addr);
+
+ //printf("\nread_raw_dboard_eeprom: %d\n", s);
+
+ switch (s){
+ case UDBE_OK:
+ return (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
+
+ case UDBE_NO_EEPROM:
+ default:
+ return -1;
+
+ case UDBE_INVALID_EEPROM:
+ return -2;
+ }
+}
+
+
+static struct db_base *
+lookup_dbid(int dbid)
+{
+ if (dbid < 0)
+ return 0;
+
+ int i;
+ for (i = 0; all_dboards[i]; i++)
+ if (all_dboards[i]->dbid == dbid)
+ return all_dboards[i];
+
+ return 0;
+}
+
+static struct db_base *
+lookup_dboard(int i2c_addr, struct db_base *default_db, char *msg)
+{
+ struct db_base *db;
+ int dbid = read_dboard_eeprom(i2c_addr);
+
+ // FIXME removing this printf has the system hang if there are two d'boards
+ // installed. (I think the problem is in i2c_read/write or the way
+ // I kludge the zero-byte write to set the read address in eeprom_read.)
+ printf("%s dbid: 0x%x\n", msg, dbid);
+
+ if (dbid < 0){ // there was some kind of problem. Treat as Basic Tx
+ return default_db;
+ }
+ else if ((db = lookup_dbid(dbid)) == 0){
+ printf("No daugherboard code for dbid = 0x%x\n", dbid);
+ return default_db;
+ }
+ return db;
+}
+
+void
+set_atr_regs(int bank, struct db_base *db)
+{
+ uint32_t val[4];
+ int shift;
+ int mask;
+ int i;
+
+ val[ATR_IDLE] = db->atr_rxval;
+ val[ATR_RX] = db->atr_rxval;
+ val[ATR_TX] = db->atr_txval;
+ val[ATR_FULL] = db->atr_txval;
+
+ if (bank == GPIO_TX_BANK){
+ mask = 0xffff0000;
+ shift = 16;
+ }
+ else {
+ mask = 0x0000ffff;
+ shift = 0;
+ }
+
+ for (i = 0; i < 4; i++){
+ int t = (atr_regs->v[i] & ~mask) | ((val[i] << shift) & mask);
+ //printf("atr_regs[%d] = 0x%x\n", i, t);
+ atr_regs->v[i] = t;
+ }
+}
+
+static void
+set_gpio_mode(int bank, struct db_base *db)
+{
+ int i;
+
+ hal_gpio_set_ddr(bank, db->output_enables, 0xffff);
+ set_atr_regs(bank, db);
+
+ for (i = 0; i < 16; i++){
+ if (db->used_pins & (1 << i)){
+ // set to either GPIO_SEL_SW or GPIO_SEL_ATR
+ hal_gpio_set_sel(bank, i, (db->atr_mask & (1 << i)) ? 'a' : 's');
+ }
+ }
+}
+
+static int __attribute__((unused))
+determine_tx_mux_value(struct db_base *db)
+{
+ if (db->i_and_q_swapped)
+ return 0x01;
+ else
+ return 0x10;
+}
+
+static int
+determine_rx_mux_value(struct db_base *db)
+{
+#define ADC0 0x0
+#define ADC1 0x1
+#define ZERO 0x2
+
+ static int truth_table[8] = {
+ /* swap_iq, uses */
+ /* 0, 0x0 */ (ZERO << 2) | ZERO, // N/A
+ /* 0, 0x1 */ (ZERO << 2) | ADC0,
+ /* 0, 0x2 */ (ZERO << 2) | ADC1,
+ /* 0, 0x3 */ (ADC1 << 2) | ADC0,
+ /* 1, 0x0 */ (ZERO << 2) | ZERO, // N/A
+ /* 1, 0x1 */ (ZERO << 2) | ADC0,
+ /* 1, 0x2 */ (ZERO << 2) | ADC1,
+ /* 1, 0x3 */ (ADC0 << 2) | ADC1,
+ };
+
+ int subdev0_uses;
+ int subdev1_uses;
+ int uses;
+
+ if (db->is_quadrature)
+ subdev0_uses = 0x3; // uses A/D 0 and 1
+ else
+ subdev0_uses = 0x1; // uses A/D 0 only
+
+ // FIXME second subdev on Basic Rx, LF RX
+ // if subdev2 exists
+ // subdev1_uses = 0x2;
+ subdev1_uses = 0;
+
+ uses = subdev0_uses;
+
+ int swap_iq = db->i_and_q_swapped & 0x1;
+ int index = (swap_iq << 2) | uses;
+
+ return truth_table[index];
+}
+
+
+void
+db_init(void)
+{
+ int m;
+
+ tx_dboard = lookup_dboard(I2C_ADDR_TX_A, &db_basic_tx, "Tx");
+ //printf("db_init: tx dbid = 0x%x\n", tx_dboard->dbid);
+ set_gpio_mode(GPIO_TX_BANK, tx_dboard);
+ tx_dboard->init(tx_dboard);
+ m = determine_tx_mux_value(tx_dboard);
+ dsp_tx_regs->tx_mux = m;
+ //printf("tx_mux = 0x%x\n", m);
+ tx_dboard->current_lo_offset = tx_dboard->default_lo_offset;
+
+ rx_dboard = lookup_dboard(I2C_ADDR_RX_A, &db_basic_rx, "Rx");
+ //printf("db_init: rx dbid = 0x%x\n", rx_dboard->dbid);
+ set_gpio_mode(GPIO_RX_BANK, rx_dboard);
+ rx_dboard->init(rx_dboard);
+ m = determine_rx_mux_value(rx_dboard);
+ dsp_rx_regs->rx_mux = m;
+ //printf("rx_mux = 0x%x\n", m);
+ rx_dboard->current_lo_offset = rx_dboard->default_lo_offset;
+}
+
+/*!
+ * Calculate the frequency to use for setting the digital down converter.
+ *
+ * \param[in] target_freq desired RF frequency (Hz)
+ * \param[in] baseband_freq the RF frequency that corresponds to DC in the IF.
+ *
+ * \param[out] dxc_freq is the value for the ddc
+ * \param[out] inverted is true if we're operating in an inverted Nyquist zone.
+*/
+void
+calc_dxc_freq(u2_fxpt_freq_t target_freq, u2_fxpt_freq_t baseband_freq,
+ u2_fxpt_freq_t *dxc_freq, bool *inverted)
+{
+ u2_fxpt_freq_t fs = U2_DOUBLE_TO_FXPT_FREQ(100e6); // converter sample rate
+ u2_fxpt_freq_t delta = target_freq - baseband_freq;
+
+#if 0
+ printf("calc_dxc_freq\n");
+ printf(" fs = "); print_fxpt_freq(fs); newline();
+ printf(" target = "); print_fxpt_freq(target_freq); newline();
+ printf(" baseband = "); print_fxpt_freq(baseband_freq); newline();
+ printf(" delta = "); print_fxpt_freq(delta); newline();
+#endif
+
+ if (delta >= 0){
+ while (delta > fs)
+ delta -= fs;
+ if (delta <= fs/2){ // non-inverted region
+ *dxc_freq = -delta;
+ *inverted = false;
+ }
+ else { // inverted region
+ *dxc_freq = delta - fs;
+ *inverted = true;
+ }
+ }
+ else {
+ while (delta < -fs)
+ delta += fs;
+ if (delta >= -fs/2){ // non-inverted region
+ *dxc_freq = -delta;
+ *inverted = false;
+ }
+ else { // inverted region
+ *dxc_freq = delta + fs;
+ *inverted = true;
+ }
+ }
+}
+
+bool
+db_set_lo_offset(struct db_base *db, u2_fxpt_freq_t offset)
+{
+ db->current_lo_offset = offset;
+ return true;
+}
+
+bool
+db_tune(struct db_base *db, u2_fxpt_freq_t target_freq, struct tune_result *result)
+{
+ memset(result, 0, sizeof(*result));
+ bool inverted = false;
+ u2_fxpt_freq_t dxc_freq;
+ u2_fxpt_freq_t actual_dxc_freq;
+
+ // Ask the d'board to tune as closely as it can to target_freq+lo_offset
+ bool ok = db->set_freq(db, target_freq+db->current_lo_offset, &result->baseband_freq);
+
+ // Calculate the DDC setting that will downconvert the baseband from the
+ // daughterboard to our target frequency.
+ calc_dxc_freq(target_freq, result->baseband_freq, &dxc_freq, &inverted);
+
+ // If the spectrum is inverted, and the daughterboard doesn't do
+ // quadrature downconversion, we can fix the inversion by flipping the
+ // sign of the dxc_freq... (This only happens using the basic_rx board)
+
+ if (db->spectrum_inverted)
+ inverted = !inverted;
+
+ if (inverted && !db->is_quadrature){
+ dxc_freq = -dxc_freq;
+ inverted = !inverted;
+ }
+
+ if (db->is_tx){
+ dxc_freq = -dxc_freq; // down conversion versus up conversion
+ ok &= db_set_duc_freq(dxc_freq, &actual_dxc_freq);
+ }
+ else {
+ ok &= db_set_ddc_freq(dxc_freq, &actual_dxc_freq);
+ }
+
+ result->dxc_freq = dxc_freq;
+ result->residual_freq = dxc_freq - actual_dxc_freq;
+ result->inverted = inverted;
+ return ok;
+}
+
+static int32_t
+compute_freq_control_word(u2_fxpt_freq_t target_freq, u2_fxpt_freq_t *actual_freq)
+{
+ // If we were using floating point, we'd calculate
+ // master = 100e6;
+ // v = (int) rint(target_freq / master_freq) * pow(2.0, 32.0);
+
+ //printf("compute_freq_control_word\n");
+ //printf(" target_freq = "); print_fxpt_freq(target_freq); newline();
+
+ int32_t master_freq = 100000000; // 100M
+
+ int32_t v = ((target_freq << 12)) / master_freq;
+ //printf(" fcw = %d\n", v);
+
+ *actual_freq = (v * (int64_t) master_freq) >> 12;
+
+ //printf(" actual = "); print_fxpt_freq(*actual_freq); newline();
+
+ return v;
+}
+
+
+bool
+db_set_ddc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq)
+{
+ int32_t v = compute_freq_control_word(dxc_freq, actual_dxc_freq);
+ dsp_rx_regs->freq = v;
+ return true;
+}
+
+bool
+db_set_duc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq)
+{
+ int32_t v = compute_freq_control_word(dxc_freq, actual_dxc_freq);
+ dsp_tx_regs->freq = v;
+ return true;
+}
+
+bool
+db_set_gain(struct db_base *db, u2_fxpt_gain_t gain)
+{
+ return db->set_gain(db, gain);
+}
+
+bool
+db_set_antenna(struct db_base *db, int ant)
+{
+ if (db->set_antenna == 0) return false;
+ return db->set_antenna(db, ant);
+}
diff --git a/usrp2/firmware/lib/db_rfx.c b/usrp2/firmware/lib/db_rfx.c
index ff12f9e32..546559010 100644
--- a/usrp2/firmware/lib/db_rfx.c
+++ b/usrp2/firmware/lib/db_rfx.c
@@ -157,6 +157,7 @@ struct db_rfx_400_rx db_rfx_400_rx = {
.base.atr_rxval = POWER_UP|MIX_EN,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 0,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -188,6 +189,7 @@ struct db_rfx_400_tx db_rfx_400_tx = {
.base.atr_rxval = POWER_UP|ANT_SW,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 1,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -218,6 +220,7 @@ struct db_rfx_900_rx db_rfx_900_rx = {
.base.atr_rxval = MIX_EN,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 1,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -249,6 +252,7 @@ struct db_rfx_900_tx db_rfx_900_tx = {
.base.atr_rxval = ANT_SW,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 1,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -279,6 +283,7 @@ struct db_rfx_1200_rx db_rfx_1200_rx = {
.base.atr_rxval = MIX_EN,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 1,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -310,6 +315,7 @@ struct db_rfx_1200_tx db_rfx_1200_tx = {
.base.atr_rxval = ANT_SW,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 1,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -340,6 +346,7 @@ struct db_rfx_1800_rx db_rfx_1800_rx = {
.base.atr_rxval = MIX_EN,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 0,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -371,6 +378,7 @@ struct db_rfx_1800_tx db_rfx_1800_tx = {
.base.atr_rxval = ANT_SW,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 0,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -402,6 +410,7 @@ struct db_rfx_2400_rx db_rfx_2400_rx = {
.base.atr_rxval = MIX_EN,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 0,
.common.CP1 = 7,
.common.CP2 = 7,
@@ -433,6 +442,7 @@ struct db_rfx_2400_tx db_rfx_2400_tx = {
.base.atr_rxval = ANT_SW,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.DIV2 = 0,
.common.CP1 = 7,
.common.CP2 = 7,
diff --git a/usrp2/firmware/lib/db_tvrx.c b/usrp2/firmware/lib/db_tvrx.c
index 49bf75883..077e59e88 100644
--- a/usrp2/firmware/lib/db_tvrx.c
+++ b/usrp2/firmware/lib/db_tvrx.c
@@ -97,6 +97,7 @@ struct db_tvrx1 db_tvrx1 = {
.base.atr_rxval = 0,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.first_if = U2_DOUBLE_TO_FXPT_FREQ(43.75e6),
.common.second_if = U2_DOUBLE_TO_FXPT_FREQ(5.75e6),
};
@@ -125,6 +126,7 @@ struct db_tvrx2 db_tvrx2 = {
.base.atr_rxval = 0,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.first_if = U2_DOUBLE_TO_FXPT_FREQ(44e6),
.common.second_if = U2_DOUBLE_TO_FXPT_FREQ(56e6), // Fs - 44e6
};
@@ -153,6 +155,7 @@ struct db_tvrx3 db_tvrx3 = {
.base.atr_rxval = 0,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.first_if = U2_DOUBLE_TO_FXPT_FREQ(44e6),
.common.second_if = U2_DOUBLE_TO_FXPT_FREQ(56e6), // Fs - 44e6
};
diff --git a/usrp2/firmware/lib/db_wbxng.c b/usrp2/firmware/lib/db_wbxng.c
index c02a5bdaa..954633da2 100644
--- a/usrp2/firmware/lib/db_wbxng.c
+++ b/usrp2/firmware/lib/db_wbxng.c
@@ -29,6 +29,9 @@
#include <stdio.h>
#include <stdint.h>
+#define min(X,Y) ((X) < (Y) ? (X) : (Y))
+#define max(X,Y) ((X) > (Y) ? (X) : (Y))
+
bool wbxng_init_rx(struct db_base *dbb);
bool wbxng_init_tx(struct db_base *dbb);
bool wbxng_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
@@ -45,7 +48,7 @@ struct db_wbxng_rx db_wbxng_rx = {
.base.is_tx = false,
.base.output_enables = RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5|PLL_CE|PLL_PDBRF|ATTN_MASK,
.base.used_pins = 0xFFFF,
- .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(67.5e6),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(68.75e6),
.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2200e6),
.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(31.5),
@@ -63,6 +66,7 @@ struct db_wbxng_rx db_wbxng_rx = {
.base.atr_rxval = RXBB_EN,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.adf4350_regs_int = UINT16_C(100),
.common.adf4350_regs_frac = 0,
.common.adf4350_regs_prescaler = 1,
@@ -80,7 +84,7 @@ struct db_wbxng_tx db_wbxng_tx = {
.base.is_tx = true,
.base.output_enables = RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5|PLL_CE|PLL_PDBRF,
.base.used_pins = 0xFFFF,
- .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(67.5e6),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(68.75e6),
.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2200e6),
.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(25),
@@ -98,6 +102,7 @@ struct db_wbxng_tx db_wbxng_tx = {
.base.atr_rxval = RX_TXN,
// .base.atr_tx_delay =
// .base.atr_rx_delay =
+ .base.set_antenna = 0,
.common.adf4350_regs_int = UINT16_C(100),
.common.adf4350_regs_frac = 0,
.common.adf4350_regs_prescaler = 1,
@@ -147,8 +152,11 @@ wbxng_init_rx(struct db_base *dbb)
bool
wbxng_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc)
{
- bool ok = adf4350_set_freq(2*freq,dbb);
- *dc = adf4350_get_freq(dbb)/2;
+ // clamp freq
+ u2_fxpt_freq_t clamp_freq = max(dbb->freq_min, min(freq, dbb->freq_max));
+ //printf("Requested LO freq = %u", (uint32_t) ((clamp_freq >> U2_FPF_RP)/1000));
+ bool ok = adf4350_set_freq(clamp_freq<<1,dbb);
+ *dc = adf4350_get_freq(dbb)>>1;
return ok;
}
diff --git a/usrp2/firmware/lib/db_xcvr2450.c b/usrp2/firmware/lib/db_xcvr2450.c
index a48af9035..4cdcf031e 100644
--- a/usrp2/firmware/lib/db_xcvr2450.c
+++ b/usrp2/firmware/lib/db_xcvr2450.c
@@ -64,6 +64,8 @@ bool xcvr2450_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *
bool xcvr2450_set_gain_rx(struct db_base *db, u2_fxpt_gain_t gain);
bool xcvr2450_set_gain_tx(struct db_base *db, u2_fxpt_gain_t gain);
bool xcvr2450_set_tx_enable(struct db_base *db, bool on);
+bool xcvr2450_set_rx_antenna(struct db_base *db, int ant);
+bool xcvr2450_set_tx_antenna(struct db_base *db, int ant);
struct db_xcvr2450_common {
int d_mimo, d_int_div, d_frac_div, d_highband, d_five_gig;
@@ -154,6 +156,7 @@ struct db_xcvr2450_rx db_xcvr2450_rx = {
.base.atr_mask = RX_ATR_MASK,
.base.atr_txval = 0x0,
.base.atr_rxval = 0x0,
+ .base.set_antenna = xcvr2450_set_rx_antenna,
.common = &db_xcvr2450_common,
};
@@ -178,6 +181,7 @@ struct db_xcvr2450_tx db_xcvr2450_tx = {
.base.atr_mask = TX_ATR_MASK,
.base.atr_txval = 0x0,
.base.atr_rxval = 0x0,
+ .base.set_antenna = xcvr2450_set_tx_antenna,
.common = &db_xcvr2450_common,
};
@@ -494,3 +498,24 @@ xcvr2450_set_tx_enable(struct db_base *dbb, bool on){
set_gpio(db);
return true;
}
+
+/**************************************************
+ * Set Antennas
+ **************************************************/
+bool xcvr2450_set_rx_antenna(struct db_base *dbb, int ant){
+ printf("xcvr set rx ant %d\n", ant);
+ if (ant > 1) return false;
+ struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
+ db->common->d_rx_ant = ant;
+ set_gpio(db);
+ return true;
+}
+
+bool xcvr2450_set_tx_antenna(struct db_base *dbb, int ant){
+ printf("xcvr set tx ant %d\n", ant);
+ if (ant > 1) return false;
+ struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
+ db->common->d_tx_ant = ant;
+ set_gpio(db);
+ return true;
+}
generated by cgit (git 2.34.1) at 2025-01-22 04:30:53 +0000