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-rw-r--r--usrp/host/lib/db_wbxng.cc82
-rw-r--r--usrp/host/lib/db_wbxng_adf4350.cc9
-rw-r--r--usrp/host/lib/db_wbxng_adf4350_regs.cc2
3 files changed, 50 insertions, 43 deletions
diff --git a/usrp/host/lib/db_wbxng.cc b/usrp/host/lib/db_wbxng.cc
index 56a8486ce..b35a9cb35 100644
--- a/usrp/host/lib/db_wbxng.cc
+++ b/usrp/host/lib/db_wbxng.cc
@@ -31,8 +31,10 @@
// Tx and Rx have shared defs, but different i/o regs
#define ENABLE_5 (1 << 7) // enables 5.0V power supply
#define ENABLE_33 (1 << 6) // enables 3.3V supply
-#define RX_TXN (1 << 5) // Tx only: T/R antenna switch for TX/RX port
-#define RX2_RX1N (1 << 5) // Rx only: antenna switch between RX2 and TX/RX port
+//#define RX_TXN (1 << 15) // Tx only: T/R antenna switch for TX/RX port
+//#define RX2_RX1N (1 << 15) // Rx only: antenna switch between RX2 and TX/RX port
+#define RX_TXN ((1 << 5)|(1 << 15)) // Tx only: T/R antenna switch for TX/RX port
+#define RX2_RX1N ((1 << 5)|(1 << 15)) // Rx only: antenna switch between RX2 and TX/RX port
#define RXBB_EN (1 << 4)
#define TXMOD_EN (1 << 4)
#define PLL_CE (1 << 3)
@@ -89,8 +91,8 @@ wbxng_base::set_freq(double freq)
t.tv_nsec = 10000000;
nanosleep(&t, NULL);
- fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
- int_freq, freq_result, d_common->_get_locked());
+ //fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n",
+ // int_freq, freq_result, d_common->_get_locked());
// FIXME
// Offsetting the LO helps get the Tx carrier leakage out of the way.
@@ -159,11 +161,13 @@ wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
d_common = new adf4350(_usrp, d_which, d_spi_enable);
- // FIXME: power up the transmit side, but don't enable the mixer
+ // power up the transmit side, but don't enable the mixer
usrp()->_write_oe(d_which,(RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
- usrp()->write_io(d_which, (power_on()|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
- fprintf(stderr,"Setting WBXNG TXMOD on");
+ usrp()->write_io(d_which, (power_on()|RX_TXN|ENABLE_33|ENABLE_5), (RX_TXN|ENABLE_33|ENABLE_5));
//set_lo_offset(4e6);
+
+ // Disable VCO/PLL
+ d_common->_enable(true);
set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
}
@@ -183,11 +187,12 @@ wbxng_base_tx::shutdown()
d_is_shutdown = true;
// do whatever there is to do to shutdown
+ // Disable VCO/PLL
+ d_common->_enable(false);
+
// Power down and leave the T/R switch in the R position
usrp()->write_io(d_which, (power_off()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
- // Power down VCO/PLL
- d_common->_enable(false);
/*
_write_control(_compute_control_reg());
@@ -202,9 +207,9 @@ wbxng_base_tx::set_auto_tr(bool on)
{
bool ok = true;
if(on) {
- ok &= set_atr_mask (RX_TXN | ENABLE_33 | ENABLE_5);
- ok &= set_atr_txval(0 | ENABLE_33 | ENABLE_5);
- ok &= set_atr_rxval(RX_TXN | 0);
+ ok &= set_atr_mask (RX_TXN | TXMOD_EN);
+ ok &= set_atr_txval(0 | TXMOD_EN);
+ ok &= set_atr_rxval(RX_TXN);
}
else {
ok &= set_atr_mask (0);
@@ -222,12 +227,16 @@ wbxng_base_tx::set_enable(bool on)
*/
int v;
- int mask = RX_TXN | ENABLE_5 | ENABLE_33;
+ int mask = RX_TXN | TXMOD_EN;
if(on) {
- v = ENABLE_5 | ENABLE_33;
+ v = TXMOD_EN;
+ // Enable VCO/PLL
+ //d_common->_enable(true);
}
else {
v = RX_TXN;
+ // Disable VCO/PLL
+ //d_common->_enable(false);
}
return usrp()->write_io(d_which, v, mask);
}
@@ -235,19 +244,19 @@ wbxng_base_tx::set_enable(bool on)
float
wbxng_base_tx::gain_min()
{
- return usrp()->pga_max();
+ return 0.0;
}
float
wbxng_base_tx::gain_max()
{
- return usrp()->pga_max() + 25.0;
+ return 25.0;
}
float
wbxng_base_tx::gain_db_per_step()
{
- return 1;
+ return gain_max()/(1+(1.4-0.5)*4096/3.3);
}
bool
@@ -266,28 +275,22 @@ wbxng_base_tx::set_gain(float gain)
float pga_gain, agc_gain;
float V_maxgain, V_mingain, V_fullscale, dac_value;
- float maxgain = gain_max() - usrp()->pga_max();
+ float maxgain = gain_max();
float mingain = gain_min();
- if(gain > maxgain) {
- pga_gain = gain-maxgain;
- assert(pga_gain <= usrp()->pga_max());
- agc_gain = maxgain;
- }
- else {
- pga_gain = 0;
- agc_gain = gain;
- }
+ pga_gain = 0;
+ agc_gain = gain;
- V_maxgain = 0.7;
+ V_maxgain = 0.5;
V_mingain = 1.4;
V_fullscale = 3.3;
dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale;
- fprintf(stderr, "TXGAIN: %f dB, Dac Code: %d, Voltage: %f\n", gain, int(dac_value), float((dac_value/4096.0)*V_fullscale));
+ //fprintf(stderr, "TXGAIN: %f dB, Dac Code: %d, Voltage: %f\n", gain, int(dac_value), float((dac_value/4096.0)*V_fullscale));
assert(dac_value>=0 && dac_value<4096);
return (usrp()->write_aux_dac(d_which, 0, int(dac_value))
- && _set_pga(int(pga_gain)));
+ && _set_pga(usrp()->pga_max()));
+
}
@@ -310,10 +313,13 @@ wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
}
d_common = new adf4350(_usrp, d_which, d_spi_enable);
+
+ // Disable VCO/PLL
+ d_common->_enable(true);
usrp()->_write_oe(d_which, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
usrp()->write_io(d_which, (power_on()|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
- fprintf(stderr,"Setting WBXNG RXBB on");
+ //fprintf(stderr,"Setting WBXNG RXBB on");
// set up for RX on TX/RX port
select_rx_antenna("TX/RX");
@@ -339,9 +345,6 @@ wbxng_base_rx::shutdown()
d_is_shutdown = true;
// do whatever there is to do to shutdown
- // Power down
- usrp()->common_write_io(C_RX, d_which, power_off(), (ENABLE_33|ENABLE_5));
-
// Power down VCO/PLL
d_common->_enable(false);
@@ -354,6 +357,9 @@ wbxng_base_rx::shutdown()
// fprintf(stderr, "wbxng_base_rx::shutdown before set_auto_tr\n");
set_auto_tr(false);
+ // Power down
+ usrp()->write_io(d_which, power_off(), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+
// fprintf(stderr, "wbxng_base_rx::shutdown after set_auto_tr\n");
}
}
@@ -363,9 +369,9 @@ wbxng_base_rx::set_auto_tr(bool on)
{
bool ok = true;
if(on) {
- ok &= set_atr_mask (ENABLE_33|ENABLE_5);
- ok &= set_atr_txval( 0);
- ok &= set_atr_rxval(ENABLE_33|ENABLE_5);
+ ok &= set_atr_mask (RXBB_EN|RX2_RX1N);
+ ok &= set_atr_txval( 0|RX2_RX1N);
+ ok &= set_atr_rxval(RXBB_EN| 0);
}
else {
ok &= set_atr_mask (0);
@@ -452,7 +458,7 @@ wbxng_base_rx::_set_attn(float attn)
{
int attn_code = int(floor(attn/0.5));
unsigned int iobits = (~attn_code) << ATTN_SHIFT;
- fprintf(stderr, "Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x \n", attn, attn_code, iobits & ATTN_MASK, ATTN_MASK);
+ //fprintf(stderr, "Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x \n", attn, attn_code, iobits & ATTN_MASK, ATTN_MASK);
return usrp()->write_io(d_which, iobits, ATTN_MASK);
}
diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc
index 2cec972b0..c17e8d670 100644
--- a/usrp/host/lib/db_wbxng_adf4350.cc
+++ b/usrp/host/lib/db_wbxng_adf4350.cc
@@ -26,9 +26,9 @@
#include <db_base_impl.h>
#include <stdio.h>
+#define FREQ_C(freq) uint64_t(freq)
#define INPUT_REF_FREQ FREQ_C(64e6)
#define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
-#define FREQ_C(freq) uint64_t(freq)
#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ) /* input ref freq with doubler turned on */
#define MIN_INT_DIV uint16_t(23) /* minimum int divider, prescaler 4/5 only */
#define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */
@@ -55,7 +55,7 @@ adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
/* Outputs */
d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
- d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
/* Initialize the pin levels. */
_enable(true);
@@ -70,6 +70,7 @@ adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
adf4350::~adf4350()
{
+ d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
delete d_regs;
}
@@ -95,9 +96,9 @@ void
adf4350::_enable(bool enable)
{
if (enable){ /* chip enable */
- d_usrp->write_io(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, (PDB_RF_PIN), (PDB_RF_PIN));
}else{
- d_usrp->write_io(d_which, 0, (CE_PIN | PDB_RF_PIN));
+ d_usrp->write_io(d_which, 0, (PDB_RF_PIN));
}
}
diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.cc b/usrp/host/lib/db_wbxng_adf4350_regs.cc
index 696b7c1d4..bc859158e 100644
--- a/usrp/host/lib/db_wbxng_adf4350_regs.cc
+++ b/usrp/host/lib/db_wbxng_adf4350_regs.cc
@@ -11,7 +11,7 @@
/* reg 1 */
const uint16_t adf4350_regs::s_phase = 0;
/* reg 2 */
-const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0;
+const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 3;
const uint8_t adf4350_regs::s_muxout = 6;
const uint8_t adf4350_regs::s_reference_doubler = 0;
const uint8_t adf4350_regs::s_rdiv2 = 0;
generated by cgit (git 2.34.1) at 2024-12-21 14:11:23 +0000