diff options
Diffstat (limited to 'usrp/firmware/include')
| -rw-r--r-- | usrp/firmware/include/fpga_regs_common.h | 7 | ||||
| -rw-r--r-- | usrp/firmware/include/fpga_regs_common.v | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/usrp/firmware/include/fpga_regs_common.h b/usrp/firmware/include/fpga_regs_common.h index fe0c81f57..af88900f0 100644 --- a/usrp/firmware/include/fpga_regs_common.h +++ b/usrp/firmware/include/fpga_regs_common.h @@ -32,8 +32,7 @@ #define FR_TX_SAMPLE_RATE_DIV 0 #define FR_RX_SAMPLE_RATE_DIV 1 -// 2 is available. -// 3 is available. +// 2 and 3 are defined in the ATR section #define FR_MASTER_CTRL 4 // master enable and reset controls # define bmFR_MC_ENABLE_TX (1 << 0) @@ -144,4 +143,8 @@ #define FR_ATR_TXVAL_3 30 #define FR_ATR_RXVAL_3 31 +// Clock ticks to delay rising and falling edge of T/R signal +#define FR_ATR_TX_DELAY 2 +#define FR_ATR_RX_DELAY 3 + #endif /* INCLUDED_FPGA_REGS_COMMON_H */ diff --git a/usrp/firmware/include/fpga_regs_common.v b/usrp/firmware/include/fpga_regs_common.v index ee87ac025..38f9362ee 100644 --- a/usrp/firmware/include/fpga_regs_common.v +++ b/usrp/firmware/include/fpga_regs_common.v @@ -13,8 +13,7 @@ `define FR_TX_SAMPLE_RATE_DIV 7'd0 `define FR_RX_SAMPLE_RATE_DIV 7'd1 -// 2 is available. -// 3 is available. +// 2 and 3 are defined in the ATR section `define FR_MASTER_CTRL 7'd4 // master enable and reset controls @@ -112,3 +111,7 @@ `define FR_ATR_TXVAL_3 7'd30 `define FR_ATR_RXVAL_3 7'd31 +// Clock ticks to delay rising and falling edge of T/R signal +`define FR_ATR_TX_DELAY 7'd2 +`define FR_ATR_RX_DELAY 7'd3 + |