diff options
Diffstat (limited to 'usrp-hw/usrp')
| -rw-r--r-- | usrp-hw/usrp/ChangeLog | 79 | ||||
| -rw-r--r-- | usrp-hw/usrp/dboard.sch | 1604 | ||||
| -rw-r--r-- | usrp-hw/usrp/fpga.sch | 1887 | ||||
| -rw-r--r-- | usrp-hw/usrp/gnetlistrc | 3 | ||||
| -rw-r--r-- | usrp-hw/usrp/gschemrc | 3 | ||||
| -rw-r--r-- | usrp-hw/usrp/interface.sch | 450 | ||||
| -rwxr-xr-x | usrp-hw/usrp/netlist_cmd | 3 | ||||
| -rw-r--r-- | usrp-hw/usrp/power.sch | 1983 |
8 files changed, 6012 insertions, 0 deletions
diff --git a/usrp-hw/usrp/ChangeLog b/usrp-hw/usrp/ChangeLog new file mode 100644 index 000000000..36856e6be --- /dev/null +++ b/usrp-hw/usrp/ChangeLog @@ -0,0 +1,79 @@ +2004-11-22 Matt Ettus <matt@ettus.com> + + * fpga.sch : + - Added R2001-R2005. + - Jumpers to gnd for TXBLANK. + - Unpopulated resistors for redoing SPI, shared with io_tx_a/b[15] + +2004-11-03 Matt Ettus <matt@ettus.com> + + * fpga.sch : Removed J900 and J902 which were to test the FX2 bus. + The lines were just too long. + +2004-10-27 Matt Ettus <matt@ettus.com> + + * power.sch : Removed text note + + * dboard.sch : Swapped RS-232 so that each board gets a pair, shared between RX and TX + + * interface.sch : + - Removed U410 (MAX232) and associated caps + - Rerouted RS232 signals so they go out as CMOS levels + - Removed J645 which was PE[2:0] + + * fpga.sch : + - Redid FX2 bus interface probe pins on J900 + - Added J902 with FX2 data bus + +2004-10-23 Matt Ettus <matt@ettus.com> + + * netlist_cmd : + - Added command script for generating a netlist + * power.sch : + - Added J1001 for ground testpoints + - Added C0603 footprint to a bunch of caps. + +2004-10-10 Matt Ettus <matt@ettus.com> + + * fpga.sch : + - Remove io_tx_b_15 from VCXO tuning, remove R800,R803,R876,C800,C804 + - Connect X2.1 to DVDD + - Removed nets CLKOUT1_x and CLKOUT2_x + - Removed R801, R802, R857 -- CLK120 now goes straight to FPGA + - Removed J901 + - Split CLK120 into CLK_FPGA, CLK_CODEC_A, and CLK_CODEC_B, each with proper source and sink terminations. Use 50 ohm lines. + - Added R1011-R1016 and C1014-C1016 for terminations + - Added MYSTERY_SIGNAL to replace one RX_SYNC + - Moved SDO to where TX_BLANK was + - Moved SDI to one RX_SYNC + - Moved SEN_FPGA to where RESET was + + * dboard.sch : + - Removed CLKOUT1_x and CLKOUT2_x + - Removed io_[tx,rx]_x_16 which never did anything + + * interface.sch : + - Added MYSTERY_SIGNAL input to INT4 + + * power.sch : + - Removed D501 + - Added C1020 for more decoupling of 5V + - Increased value of C502 to 100 uF + +2004-10-08 Matt Ettus <matt@ettus.com> + + * interface.sch : + - Reset on PC0 is now RESET_CODEC + - Tool changed format of Text items + - NB - Need to find pin for RESET_FPGA. Maybe PE0,1,2 or FX2_1. Send rest to dboard? + + * dboard.sch : + - R701, R702 changed from 2K to 4K, to fit what the datasheet tells us. + - R1001,R1002,R1003,R1004,C1001,C1002,C1003,C1004 added to do sigma delta filtering on the motherboard + - Net SIGDEL_x no longer goes to dboard. It gets filtered, and AUX_DAC_D_x is sent + - RESET on CODECs and Dboards is now RESET_CODEC + - Tool changed format of Text items + - NB - Should we avoid sending REFIO_x to the dboards for sig integrity? + - NB - Get rid of io_tx/rx_x_16 + - NB - Find a bit 15 for io buses + diff --git a/usrp-hw/usrp/dboard.sch b/usrp-hw/usrp/dboard.sch new file mode 100644 index 000000000..3a6a9bc94 --- /dev/null +++ b/usrp-hw/usrp/dboard.sch @@ -0,0 +1,1604 @@ +v 20040111 1 +C 30600 17800 1 0 0 ad986X-ACTRL.sym +{ +T 81300 48100 5 10 1 1 0 6 1 +refdes=U602 +} +C 38400 17800 1 0 0 ad986X-AUX.sym +{ +T 89100 48100 5 10 1 1 0 6 1 +refdes=U602 +} +C 32400 13600 1 0 0 ad986X-CTRL.sym +{ +T 83200 43900 5 10 1 1 0 6 1 +refdes=U602 +} +C 79100 36200 1 270 1 pmc64.sym +{ +T 92300 36900 5 10 1 1 90 2 1 +refdes=J669 +T 79100 36200 5 10 0 1 0 0 1 +footprint=pmc +} +C 79100 31000 1 270 1 pmc64.sym +{ +T 92300 31700 5 10 1 1 90 2 1 +refdes=J668 +T 79100 31000 5 10 0 1 180 6 1 +footprint=pmc +} +C 77900 47200 1 90 1 generic-power.sym +{ +T 77650 47000 5 10 1 1 270 5 1 +net=AGND_2:1 +} +C 79200 46800 1 0 1 capacitor-1.sym +{ +T 78600 46800 5 10 1 1 0 6 1 +refdes=C714 +T 78200 47200 5 10 1 1 180 6 1 +value=0.1uF +T 79200 46800 5 10 0 1 90 2 1 +footprint=0603 +} +N 80300 47000 79200 47000 4 +N 78300 47000 77900 47000 4 +C 79200 47500 1 180 1 resistor-1.sym +{ +T 80200 47500 5 10 1 1 0 6 1 +value=4K +T 79200 47500 5 10 0 1 180 6 1 +footprint=0603 +T 79300 47500 5 10 1 1 0 6 1 +refdes=R702 +} +N 80300 47400 80100 47400 4 +N 79200 47400 78100 47400 4 +N 78100 47400 78100 47000 4 +C 84900 47000 1 270 0 generic-power.sym +{ +T 85150 46800 5 10 1 1 270 3 1 +net=AGND_2:1 +} +C 84600 46400 1 180 0 capacitor-1.sym +{ +T 83600 46300 5 10 1 1 0 0 1 +refdes=C702 +T 83600 46000 5 10 1 1 0 0 1 +value=0.1uF +T 84600 46400 5 10 0 1 270 0 1 +footprint=0603 +} +N 82300 46600 82500 46600 4 +N 82500 46600 82500 46200 4 +N 82300 46200 83700 46200 4 +N 82300 47400 83700 47400 4 +N 82500 47400 82500 47000 4 +N 82500 47000 82300 47000 4 +C 84600 47600 1 180 0 capacitor-1.sym +{ +T 83600 47500 5 10 1 1 0 0 1 +refdes=C703 +T 83600 47200 5 10 1 1 0 0 1 +value=0.1uF +T 84600 47600 5 10 0 1 270 0 1 +footprint=0603 +} +N 84700 46800 84900 46800 4 +N 84600 47400 84700 47400 4 +N 84600 46200 84700 46200 4 +C 82600 47300 1 270 0 capacitor-1.sym +{ +T 83100 47100 5 10 1 1 180 0 1 +refdes=C704 +T 83000 46300 5 10 1 1 90 0 1 +value=0.1uF +T 82600 47300 5 10 0 1 0 0 1 +footprint=0603 +} +C 83100 47300 1 270 0 capacitor-1.sym +{ +T 83600 47100 5 10 1 1 180 0 1 +refdes=C705 +T 83500 46300 5 10 1 1 90 0 1 +value=10uF +T 83100 47300 5 10 0 1 0 0 1 +footprint=1206 +} +N 82800 47300 82800 47400 4 +N 83300 47300 83300 47400 4 +N 82800 46400 82800 46200 4 +N 83300 46400 83300 46200 4 +C 82500 45100 1 0 0 capacitor-1.sym +{ +T 82400 45500 5 10 1 1 0 0 1 +refdes=C706 +T 83500 45500 5 10 1 1 180 0 1 +value=0.1uF +T 82500 45100 5 10 0 1 90 0 1 +footprint=0603 +} +C 82500 45600 1 0 0 capacitor-1.sym +{ +T 82400 45900 5 10 1 1 0 0 1 +refdes=C707 +T 83500 46000 5 10 1 1 180 0 1 +value=10uF +T 82500 45600 5 10 0 1 90 0 1 +footprint=1206 +} +N 83400 45300 83600 45300 4 +N 83600 45300 83600 45800 4 +N 82500 45800 82300 45800 4 +N 82500 45300 82400 45300 4 +N 83400 45800 84700 45800 4 +N 84700 45800 84700 47400 4 +N 83800 32500 83800 36300 4 +{ +T 83800 33700 5 10 1 1 90 0 1 +netname=RS232_TXD_2 +} +N 82600 32500 82600 36300 4 +{ +T 82600 34200 5 10 1 1 90 0 1 +netname=SDA +} +N 82200 32500 82200 36300 4 +{ +T 82200 34200 5 10 1 1 90 0 1 +netname=SCL +} +C 92000 30900 1 180 0 generic-power.sym +{ +T 91800 30650 5 10 1 1 180 3 1 +net=AGND_2:1 +} +C 81200 35800 1 180 0 generic-power.sym +{ +T 81000 35550 5 10 1 1 180 3 1 +net=DVDD:1 +} +N 91800 30900 91800 31100 4 +C 83300 35500 1 0 0 gnd-1.sym +N 83000 35800 83000 36300 4 +N 83400 35800 83400 36300 4 +N 83000 32500 83000 33000 4 +N 83400 32500 83400 33000 4 +C 83200 33000 1 0 0 generic-power.sym +{ +T 83400 33250 5 10 1 1 0 3 1 +net=DVDD:1 +} +T 83300 34000 9 10 1 0 90 0 1 +I2C Address +C 79500 33100 1 180 0 gnd-1.sym +N 79400 32500 79400 32800 4 +C 79500 38300 1 180 0 gnd-1.sym +N 79400 37700 79400 38000 4 +C 79300 35700 1 0 0 gnd-1.sym +N 79400 36300 79400 36000 4 +C 79300 30500 1 0 0 gnd-1.sym +N 79400 31100 79400 30800 4 +C 92000 36100 1 180 0 generic-power.sym +{ +T 91800 35850 5 10 1 1 180 3 1 +net=AGND_2:1 +} +N 91800 36100 91800 36300 4 +C 91600 32700 1 0 0 generic-power.sym +{ +T 91800 32950 5 10 1 1 0 3 1 +net=AGND_2:1 +} +N 91800 32700 91800 32500 4 +N 85000 32500 85000 36300 4 +{ +T 85000 34300 5 10 1 1 90 0 1 +netname=SCLK +} +N 84600 32500 84600 36300 4 +{ +T 84600 33700 5 10 1 1 90 0 1 +netname=RESET_CODEC +} +N 85400 32500 85400 36300 4 +{ +T 85400 34300 5 10 1 1 90 0 1 +netname=SDO +} +N 86200 35100 86200 36300 4 +{ +T 86200 35200 5 10 1 1 90 0 1 +netname=SEN_TX_B +} +N 86200 32500 86200 33700 4 +{ +T 86200 32600 5 10 1 1 90 0 1 +netname=SEN_RX_B +} +C 86500 30600 1 0 0 gnd-1.sym +N 86600 31100 86600 30900 4 +C 86700 38200 1 180 0 gnd-1.sym +N 86600 37700 86600 37900 4 +C 86500 35800 1 0 0 gnd-1.sym +N 86600 36300 86600 36100 4 +C 86700 33000 1 180 0 gnd-1.sym +N 86600 32500 86600 32700 4 +C 87600 30900 1 180 0 generic-power.sym +{ +T 87400 30650 5 10 1 1 180 3 1 +net=AGND_2:1 +} +N 87400 30900 87400 31100 4 +C 87600 36100 1 180 0 generic-power.sym +{ +T 87400 35850 5 10 1 1 180 3 1 +net=AGND_2:1 +} +N 87400 36100 87400 36300 4 +C 87200 37900 1 0 0 generic-power.sym +{ +T 87400 38150 5 10 1 1 0 3 1 +net=AGND_2:1 +} +N 87400 37900 87400 37700 4 +C 87200 32700 1 0 0 generic-power.sym +{ +T 87400 32950 5 10 1 1 0 3 1 +net=AGND_2:1 +} +N 87400 32700 87400 32500 4 +N 85800 32500 85800 36300 4 +{ +T 85800 34300 5 10 1 1 90 0 1 +netname=SDI +} +N 89000 32500 89000 36300 4 +{ +T 89000 33800 5 10 1 1 90 0 1 +netname=AUX_DAC_D_B +} +N 89400 32500 89400 36300 4 +{ +T 89400 33800 5 10 1 1 90 0 1 +netname=AUX_DAC_A_B +} +N 89800 32500 89800 36300 4 +{ +T 89800 33800 5 10 1 1 90 0 1 +netname=AUX_DAC_B_B +} +N 90200 32500 90200 36300 4 +{ +T 90200 33800 5 10 1 1 90 0 1 +netname=AUX_DAC_C_B +} +N 91000 34700 91000 36300 4 +{ +T 91000 34700 5 10 1 1 90 0 1 +netname=AUX_ADC_A2_B +} +N 90600 32500 90600 36300 4 +{ +T 90600 33700 5 10 1 1 90 0 1 +netname=AUX_ADC_REF_B +} +N 91000 32500 91000 34100 4 +{ +T 91000 32500 5 10 1 1 90 0 1 +netname=AUX_ADC_A1_B +} +N 91400 34700 91400 36300 4 +{ +T 91400 34700 5 10 1 1 90 0 1 +netname=AUX_ADC_B2_B +} +N 91400 32500 91400 34100 4 +{ +T 91400 32500 5 10 1 1 90 0 1 +netname=AUX_ADC_B1_B +} +C 90800 30900 1 180 0 generic-power.sym +{ +T 90600 30650 5 10 1 1 180 3 1 +net=AGND_2:1 +} +N 90600 30900 90600 31100 4 +C 90000 30900 1 180 0 generic-power.sym +{ +T 89800 30650 5 10 1 1 180 3 1 +net=AGND_2:1 +} +N 89800 30900 89800 31100 4 +C 88800 30900 1 180 0 generic-power.sym +{ +T 88600 30650 5 10 1 1 180 3 1 +net=AGND_2:1 +} +N 88600 30900 88600 31100 4 +N 91400 29500 91400 31100 4 +{ +T 91400 29500 5 10 1 1 90 0 1 +netname=VINP_A_B +} +N 91000 29500 91000 31100 4 +{ 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+} +C 88000 30300 1 180 1 generic-power.sym +{ +T 88200 30050 5 10 1 1 180 3 1 +net=AVDD_2:1 +} +N 88200 31100 88200 30300 4 +N 87800 31100 87800 30600 4 +C 87600 30600 1 180 1 generic-power.sym +{ +T 87800 30350 5 10 1 1 180 3 1 +net=AVDD_2:1 +} +N 88200 37700 88200 38500 4 +N 87800 37700 87800 38200 4 +C 87600 38200 1 0 0 generic-power.sym +{ +T 87800 38450 5 10 1 1 0 3 1 +net=AVDD_2:1 +} +C 88000 38500 1 0 0 generic-power.sym +{ +T 88200 38750 5 10 1 1 0 3 1 +net=AVDD_2:1 +} +N 79800 32500 79800 33200 4 +N 80200 32500 80200 33000 4 +N 80200 36300 80200 36000 4 +N 79800 36300 79800 35600 4 +C 80000 35600 1 180 0 generic-power.sym +{ +T 79800 35350 5 10 1 1 180 3 1 +net=5V:1 +} +C 80800 33000 1 0 0 generic-power.sym +{ +T 81000 33250 5 10 1 1 0 3 1 +net=DVDD:1 +} +N 81000 32500 81000 33000 4 +N 81000 35800 81000 36300 4 +N 90900 47400 92500 47400 4 +{ +T 91200 47400 5 10 1 1 0 0 1 +netname=SIGDEL_B +} +N 90900 47000 92500 47000 4 +{ +T 91000 47000 5 10 1 1 0 0 1 +netname=AUX_DAC_A_B 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270 5 1 +net=AGND_1:1 +} +C 63100 46800 1 0 1 capacitor-1.sym +{ +T 62500 46800 5 10 1 1 0 6 1 +refdes=C701 +T 62100 47200 5 10 1 1 180 6 1 +value=0.1uF +T 63100 46800 5 10 0 1 90 2 1 +footprint=0603 +} +N 64200 47000 63100 47000 4 +N 62200 47000 61800 47000 4 +C 63100 47500 1 180 1 resistor-1.sym +{ +T 64100 47500 5 10 1 1 0 6 1 +value=4K +T 63100 47500 5 10 0 1 180 6 1 +footprint=0603 +T 63300 47500 5 10 1 1 0 6 1 +refdes=R701 +} +N 64200 47400 64000 47400 4 +N 63100 47400 62000 47400 4 +N 62000 47400 62000 47000 4 +C 68800 47000 1 270 0 generic-power.sym +{ +T 69050 46800 5 10 1 1 270 3 1 +net=AGND_1:1 +} +C 68500 46400 1 180 0 capacitor-1.sym +{ +T 67500 46300 5 10 1 1 0 0 1 +refdes=C708 +T 67500 46000 5 10 1 1 0 0 1 +value=0.1uF +T 68500 46400 5 10 0 1 270 0 1 +footprint=0603 +} +N 66200 46600 66400 46600 4 +N 66400 46600 66400 46200 4 +N 66200 46200 67600 46200 4 +N 66200 47400 67600 47400 4 +N 66400 47400 66400 47000 4 +N 66400 47000 66200 47000 4 +C 68500 47600 1 180 0 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36400 1 0 0 gnd-1.sym +N 51100 36700 51100 37000 4 +N 48700 38300 51100 38300 4 +{ +T 49900 38300 5 10 1 1 180 0 1 +netname=TXBLANK_B +} +N 51100 38300 51100 37900 4 +C 76600 42600 1 0 0 gnd-1.sym +N 76700 42900 76700 43100 4 +N 76700 44000 76700 44300 4 +C 53200 50000 1 0 1 resistor-1.sym +{ +T 52700 50300 5 10 1 1 90 2 1 +refdes=R2004 +T 53200 50000 5 10 0 1 180 2 1 +footprint=0603 +T 53000 50300 5 10 1 1 90 0 1 +value=NONE +} +N 53200 50100 53400 50100 4 +N 53400 50100 53400 49600 4 +N 60100 38600 61700 38600 4 +{ +T 60500 38600 5 10 1 1 0 0 1 +netname=SCLK +} +N 69700 54700 71300 54700 4 +{ +T 71200 54700 5 10 1 1 0 6 1 +netname=SEN_CODEC_A +} +C 51200 40400 1 270 1 resistor-1.sym +{ +T 51500 40900 5 10 1 1 0 2 1 +refdes=R2005 +T 51200 40400 5 10 0 1 90 2 1 +footprint=0603 +T 51500 40600 5 10 1 1 0 0 1 +value=NONE +} +N 51300 40400 51300 38800 4 +{ +T 51300 38900 5 10 1 1 90 0 1 +netname=SEN_CODEC_B +} +N 51300 41300 51300 41600 4 +N 51300 41600 53400 41600 4 +{ +T 52200 41600 5 10 1 1 0 0 1 +netname=io_tx_b_15 +} +N 68300 52100 68300 54700 4 +{ +T 68300 52900 5 10 1 1 90 0 1 +netname=io_tx_a_15 +} +N 68300 54700 68800 54700 4 +C 61100 46000 1 0 0 SMA-5.sym +{ +T 61100 46800 5 10 1 1 0 0 1 +refdes=J2001 +T 61100 46000 5 10 0 1 0 6 1 +footprint=SMA_VERT +} +C 62900 46400 1 0 1 resistor-1.sym +{ +T 62700 46700 5 10 1 1 180 2 1 +refdes=R2027 +T 62900 46400 5 10 0 1 180 2 1 +footprint=0603 +T 62300 46200 5 10 1 1 0 0 1 +value=50 +} +N 61600 46500 62000 46500 4 +N 62900 46500 63900 46500 4 +C 61300 45500 1 0 1 gnd-1.sym +N 61200 45800 61200 46000 4 diff --git a/usrp-hw/usrp/gnetlistrc b/usrp-hw/usrp/gnetlistrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/usrp/gnetlistrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/usrp/gschemrc b/usrp-hw/usrp/gschemrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/usrp/gschemrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/usrp/interface.sch b/usrp-hw/usrp/interface.sch new file mode 100644 index 000000000..f5b72f8a1 --- /dev/null +++ b/usrp-hw/usrp/interface.sch @@ -0,0 +1,450 @@ +v 20040111 1 +C 17200 44300 1 0 0 cy7c68013-tq100-CTRL.sym +{ +T 68200 74600 5 10 1 1 0 6 1 +refdes=U412 +} +C 114700 36300 1 0 1 cy7c68013-tq100-MISC.sym +{ +T 63800 66600 5 10 1 1 0 0 1 +refdes=U412 +} +C 16300 92600 1 180 1 cy7c68013-tq100-PC.sym +{ +T 67100 66400 5 10 1 1 180 0 1 +refdes=U412 +} +C 21600 93000 1 180 1 ep1c12-pq240-CFG.sym +{ +T 72500 67200 5 10 1 1 180 0 1 +refdes=U101 +} +C 7000 97300 1 180 1 ep1c12-pq240-JTAG.sym +{ +T 57800 69500 5 10 1 1 180 0 1 +refdes=U101 +} +C 59500 65900 1 0 0 24Cxx-1.sym +{ +T 60000 67100 5 10 1 1 0 0 1 +refdes=U413 +T 59500 65900 5 10 0 1 0 0 1 +footprint=SO8 +T 59800 65700 5 10 1 1 0 0 1 +device=24LC02B +T 59800 65300 5 10 1 1 0 0 1 +net=GND:4 +T 59800 65500 5 10 1 1 0 0 1 +net=DVDD:8 +} +C 70800 66000 1 90 0 generic-power.sym +{ +T 70550 66200 5 10 1 1 90 3 1 +net=DVDD:1 +} +C 70600 65900 1 270 0 gnd-1.sym +N 71300 65800 70900 65800 4 +N 70800 66200 71300 66200 4 +C 70600 66700 1 270 0 gnd-1.sym +N 71300 66600 70900 66600 4 +N 68000 65000 71300 65000 4 +N 68000 64600 71300 64600 4 +N 68000 64200 71300 64200 4 +N 71300 63800 68000 63800 4 +N 71300 63400 68000 63400 4 +C 68800 69900 1 0 0 generic-power.sym +{ +T 69000 70150 5 10 1 1 0 3 1 +net=DVDD:1 +} +C 68000 68100 1 270 0 led-1.sym +{ +T 67600 67300 5 10 1 1 0 0 1 +refdes=D402 +} +C 68600 67500 1 270 0 led-1.sym +{ +T 68200 66700 5 10 1 1 0 0 1 +refdes=D403 +} +C 70200 67300 1 90 0 resistor-1.sym +{ +T 70500 67700 5 10 1 1 180 0 1 +value=10K +T 70200 67300 5 10 0 1 90 0 1 +footprint=0603 +T 70200 67300 5 10 1 1 0 0 1 +refdes=R101 +} +C 69900 66700 1 90 0 resistor-1.sym +{ +T 70200 67100 5 10 1 1 180 0 1 +value=10K +T 69900 66700 5 10 0 1 90 0 1 +footprint=0603 +T 69900 66700 5 10 1 1 0 0 1 +refdes=R102 +} +C 69600 67000 1 90 0 resistor-1.sym +{ +T 69300 67600 5 10 1 1 180 0 1 +value=10K +T 69600 67000 5 10 0 1 90 0 1 +footprint=0603 +T 69100 67200 5 10 1 1 0 0 1 +refdes=R104 +} +C 68900 67700 1 90 0 resistor-1.sym +{ +T 69200 68100 5 10 1 1 180 0 1 +value=1K +T 68900 67700 5 10 0 1 90 0 1 +footprint=0603 +T 68900 67700 5 10 1 1 0 0 1 +refdes=R420 +} +C 68300 68300 1 90 0 resistor-1.sym +{ +T 68600 68700 5 10 1 1 180 0 1 +value=1K +T 68300 68300 5 10 0 1 90 0 1 +footprint=0603 +T 68300 68300 5 10 1 1 0 0 1 +refdes=R422 +} +N 68200 67200 68200 65800 4 +N 68200 65800 68000 65800 4 +N 68800 66600 68800 65400 4 +N 68800 65400 68000 65400 4 +N 68200 68100 68200 68300 4 +N 68200 69200 68200 69500 4 +N 68800 69500 68800 68600 4 +N 68800 67500 68800 67700 4 +N 69500 69500 69500 67900 4 +N 69800 69500 69800 67600 4 +N 70100 68200 70100 69500 4 +N 68200 69500 70100 69500 4 +N 69000 69900 69000 69500 4 +N 69500 67000 69500 65000 4 +N 69800 66700 69800 64600 4 +N 70100 67300 70100 63800 4 +C 64200 74000 1 180 1 connector4-1.sym +{ +T 64200 72600 5 10 1 1 180 6 1 +refdes=J401 +T 64200 74000 5 10 0 1 0 0 1 +footprint=USB +} +N 65900 73500 66900 73500 4 +C 66600 73700 1 90 0 gnd-1.sym +N 65900 73800 66300 73800 4 +C 65700 71800 1 0 0 crystal-1.sym +{ +T 65900 72100 5 10 1 1 0 0 1 +refdes=X1 +T 65700 71800 5 10 0 1 0 0 1 +footprint=HC-49USMD +} +C 65300 71700 1 270 0 capacitor-1.sym +{ +T 65000 70900 5 10 1 1 0 0 1 +refdes=C460 +T 65000 70700 5 10 1 1 0 0 1 +value=22pF +T 65300 71700 5 10 0 1 0 0 1 +footprint=0603 +} +C 66400 71700 1 270 0 capacitor-1.sym +{ +T 66100 70900 5 10 1 1 0 0 1 +refdes=C464 +T 66100 70700 5 10 1 1 0 0 1 +value=22pF +T 66400 71700 5 10 0 1 0 0 1 +footprint=0603 +} +C 66000 70200 1 0 0 gnd-1.sym +N 65500 70800 65500 70600 4 +N 65500 70600 66600 70600 4 +N 66600 70600 66600 70800 4 +N 66100 70500 66100 70600 4 +N 65500 71900 65700 71900 4 +N 66400 71900 66600 71900 4 +N 66600 71700 66600 72300 4 +N 66600 72300 66900 72300 4 +N 66900 72700 65500 72700 4 +N 65500 71700 65500 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+date=$Date: 2004/10/27 23:28:42 $ +T 71400 60300 5 10 1 1 0 0 1 +rev=$Revision: 1.5 $ +T 71500 60000 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 67300 60300 5 10 1 1 0 0 1 +fname=$RCSfile: interface.sch,v $ +T 70700 61000 8 14 1 1 0 4 1 +title=USRP FPGA/FX2 Interface +T 68300 60000 9 10 1 0 0 0 1 +2 +T 69100 60000 9 10 1 0 0 0 1 +4 +N 65000 64700 65500 64700 4 +N 65500 64700 65500 66800 4 +{ +T 65500 64800 5 10 1 1 90 0 1 +netname=MYSTERY_SIGNAL +} diff --git a/usrp-hw/usrp/netlist_cmd b/usrp-hw/usrp/netlist_cmd new file mode 100755 index 000000000..234de1238 --- /dev/null +++ b/usrp-hw/usrp/netlist_cmd @@ -0,0 +1,3 @@ +gnetlist -g pads -o usrp_mboard.net power.sch fpga.sch interface.sch dboard.sch +gnetlist -g partslist3 -o usrp_mboard.bom power.sch fpga.sch interface.sch dboard.sch + diff --git a/usrp-hw/usrp/power.sch b/usrp-hw/usrp/power.sch new file mode 100644 index 000000000..57cebf365 --- /dev/null +++ b/usrp-hw/usrp/power.sch @@ -0,0 +1,1983 @@ +v 20040111 1 +C 26600 109300 1 270 0 cy7c68013-tq100-PWR.sym +{ +T 56800 59800 5 10 1 1 0 6 1 +refdes=U412 +} +C 39900 103800 1 270 0 ep1c12-pq240-PWR.sym +{ +T 70200 54000 5 10 1 1 0 6 1 +refdes=U101 +} +C 23100 31000 1 0 0 tps777xx-pwp.sym +{ +T 74200 61200 5 10 1 1 0 6 1 +refdes=U503 +} +C 15900 27600 1 0 0 lt1085.sym +{ +T 66900 57800 5 10 1 1 0 6 1 +refdes=U502 +T 15900 27600 5 10 0 1 0 0 1 +footprint=LT1085 +} +C 59800 56800 1 0 0 connector3-1.sym +{ +T 59800 57900 5 10 1 1 0 0 1 +refdes=J502 +T 59800 56800 5 10 0 1 0 0 1 +footprint=RAPC722 +} +C 61700 55800 1 0 0 gnd-1.sym +N 61800 56100 61800 57300 4 +N 61500 57000 61800 57000 4 +C 61700 57600 1 0 0 fuse-1.sym +{ +T 61900 57800 5 10 1 1 0 0 1 +refdes=F501 +T 61700 57600 5 10 0 1 0 0 1 +footprint=0603 +} +N 61500 57600 61700 57600 4 +N 61500 57300 61800 57300 4 +N 63700 57600 63700 58000 4 +C 64600 57400 1 270 0 capacitor-1.sym +{ +T 64300 56600 5 10 1 1 0 0 1 +refdes=C510 +T 64300 56400 5 10 1 1 0 0 1 +value=0.1uF +T 64600 57400 5 10 0 1 0 0 1 +footprint=0603 +} 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