diff options
Diffstat (limited to 'gr-uhd/include')
| -rw-r--r-- | gr-uhd/include/gr_uhd_usrp_sink.h | 22 | ||||
| -rw-r--r-- | gr-uhd/include/gr_uhd_usrp_source.h | 36 |
2 files changed, 57 insertions, 1 deletions
diff --git a/gr-uhd/include/gr_uhd_usrp_sink.h b/gr-uhd/include/gr_uhd_usrp_sink.h index ce76ec03b..ff4856f9b 100644 --- a/gr-uhd/include/gr_uhd_usrp_sink.h +++ b/gr-uhd/include/gr_uhd_usrp_sink.h @@ -118,6 +118,19 @@ class GR_UHD_API uhd_usrp_sink : virtual public gr_sync_block{ public: /*! + * Set the start time for outgoing samples. + * To control when samples are transmitted, + * set this value before starting the flow graph. + * The value is cleared after each run. + * When not specified, the start time will be: + * - Immediately for the one channel case + * - in the near future for multi-channel + * + * \param time the absolute time for transmission to begin + */ + virtual void set_start_time(const uhd::time_spec_t &time) = 0; + + /*! * Set the frontend specification. * \param spec the subdev spec markup string * \param mboard the motherboard index 0 to M-1 @@ -448,6 +461,15 @@ public: * \return the multi usrp device object */ virtual uhd::usrp::multi_usrp::sptr get_device(void) = 0; + + /*! + * Perform write on the user configuration register bus. These only exist if + * the user has implemented custom setting registers in the device FPGA. + * \param addr 8-bit register address + * \param data 32-bit register value + * \param mboard which motherboard to set the user register + */ + virtual void set_user_register(const uint8_t addr, const uint32_t data, size_t mboard = 0) = 0; }; #endif /* INCLUDED_GR_UHD_USRP_SINK_H */ diff --git a/gr-uhd/include/gr_uhd_usrp_source.h b/gr-uhd/include/gr_uhd_usrp_source.h index c33eb2a6f..415503bc1 100644 --- a/gr-uhd/include/gr_uhd_usrp_source.h +++ b/gr-uhd/include/gr_uhd_usrp_source.h @@ -110,6 +110,19 @@ class GR_UHD_API uhd_usrp_source : virtual public gr_sync_block{ public: /*! + * Set the start time for incoming samples. + * To control when samples are received, + * set this value before starting the flow graph. + * The value is cleared after each run. + * When not specified, the start time will be: + * - Immediately for the one channel case + * - in the near future for multi-channel + * + * \param time the absolute time for reception to begin + */ + virtual void set_start_time(const uhd::time_spec_t &time) = 0; + + /*! * Set the frontend specification. * \param spec the subdev spec markup string * \param mboard the motherboard index 0 to M-1 @@ -457,13 +470,34 @@ public: virtual uhd::usrp::multi_usrp::sptr get_device(void) = 0; /*! + * Perform write on the user configuration register bus. These only exist if + * the user has implemented custom setting registers in the device FPGA. + * \param addr 8-bit register address + * \param data 32-bit register value + * \param mboard which motherboard to set the user register + */ + virtual void set_user_register(const uint8_t addr, const uint32_t data, size_t mboard = 0) = 0; + + /*! * Convenience function for finite data acquisition. * This is not to be used with the scheduler; rather, * one can request samples from the USRP in python. - * //TODO multi-channel * //TODO assumes fc32 + * \param nsamps the number of samples + * \return a vector of complex float samples */ virtual std::vector<std::complex<float> > finite_acquisition(const size_t nsamps) = 0; + + /*! + * Convenience function for finite data acquisition. + * This is the multi-channel version of finite_acquisition; + * This is not to be used with the scheduler; rather, + * one can request samples from the USRP in python. + * //TODO assumes fc32 + * \param nsamps the number of samples per channel + * \return a vector of buffers, where each buffer represents a channel + */ + virtual std::vector<std::vector<std::complex<float> > > finite_acquisition_v(const size_t nsamps) = 0; }; #endif /* INCLUDED_GR_UHD_USRP_SOURCE_H */ |