diff options
Diffstat (limited to 'gr-radar-mono/src')
51 files changed, 0 insertions, 4072 deletions
diff --git a/gr-radar-mono/src/.gitignore b/gr-radar-mono/src/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/Makefile.am b/gr-radar-mono/src/Makefile.am deleted file mode 100644 index d546da7f8..000000000 --- a/gr-radar-mono/src/Makefile.am +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = fpga lib -if PYTHON -SUBDIRS += python -endif diff --git a/gr-radar-mono/src/fpga/.gitignore b/gr-radar-mono/src/fpga/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/fpga/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/Makefile.am b/gr-radar-mono/src/fpga/Makefile.am deleted file mode 100644 index fb2a09c9c..000000000 --- a/gr-radar-mono/src/fpga/Makefile.am +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = lib top tb models diff --git a/gr-radar-mono/src/fpga/lib/.gitignore b/gr-radar-mono/src/fpga/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/fpga/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am deleted file mode 100644 index e97ff1b6a..000000000 --- a/gr-radar-mono/src/fpga/lib/Makefile.am +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - radar.v \ - radar_config.vh \ - radar_control.v \ - radar_tx.v \ - radar_rx.v \ - dac_interface.v \ - fifo32_2k.v \ - cordic_nco.v - -MOSTLYCLEANFILES += *.bak diff --git a/gr-radar-mono/src/fpga/lib/cordic_nco.v b/gr-radar-mono/src/fpga/lib/cordic_nco.v deleted file mode 100644 index b9858baf8..000000000 --- a/gr-radar-mono/src/fpga/lib/cordic_nco.v +++ /dev/null @@ -1,54 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module cordic_nco(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,phs_i,data_i_o,data_q_o); - input clk_i; - input rst_i; - input ena_i; - input strobe_i; - - input [15:0] ampl_i; - input [31:0] freq_i; - input [31:0] phs_i; - - output [15:0] data_i_o; - output [15:0] data_q_o; - - reg [31:0] phase_reg; - wire [31:0] phase = phase_reg + phs_i; - wire [15:0] ampl; - - always @(posedge clk_i) - begin - if (rst_i | ~ena_i) - phase_reg <= 32'b0; - else if (strobe_i) - phase_reg <= phase_reg + freq_i; - end - - assign ampl = ena_i ? ampl_i : 16'b0; - - cordic tx_cordic - (.clock(clk_i),.reset(rst_i),.enable(strobe_i), - .xi(ampl),.yi(16'b0),.zi(phase[31:16]), - .xo(data_i_o),.yo(data_q_o),.zo()); - -endmodule // cordic_nco diff --git a/gr-radar-mono/src/fpga/lib/dac_interface.v b/gr-radar-mono/src/fpga/lib/dac_interface.v deleted file mode 100644 index 209aebd96..000000000 --- a/gr-radar-mono/src/fpga/lib/dac_interface.v +++ /dev/null @@ -1,60 +0,0 @@ -// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-`include "../top/config.vh"
-
-module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
- input clk_i;
- input rst_i;
- input ena_i;
- input strobe_i;
-
- input [13:0] tx_i_i;
- input [13:0] tx_q_i;
-
- output [13:0] tx_data_o;
- output tx_sync_o;
-
-`ifdef TX_RATE_MAX
- wire clk128;
- reg clk64_d;
- reg [13:0] tx_data_o;
-
- // Create a 128 MHz clock
- dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
-
- // Register the clk64 clock in the clk128 domain
- always @(posedge clk128)
- clk64_d <= clk_i;
-
- // Register the tx data in the clk128 domain
- always @(posedge clk128)
- tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
-
- assign tx_sync_o = clk64_d;
-
-
-`else // !`ifdef TX_RATE_MAX
- assign tx_data_o = strobe_i ? tx_i_i : tx_q_i;
- assign tx_sync_o = strobe_i;
-`endif // !`ifdef TX_RATE_MAX
-
-endmodule // dac_interface
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_2k.v b/gr-radar-mono/src/fpga/lib/fifo32_2k.v deleted file mode 100755 index c045b70e7..000000000 --- a/gr-radar-mono/src/fpga/lib/fifo32_2k.v +++ /dev/null @@ -1,161 +0,0 @@ -// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: scfifo
-
-// ============================================================
-// File Name: fifo32_2k.v
-// Megafunction Name(s):
-// scfifo
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2007 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module fifo32_2k (
- clock,
- data,
- rdreq,
- sclr,
- wrreq,
- empty,
- q);
-
- input clock;
- input [31:0] data;
- input rdreq;
- input sclr;
- input wrreq;
- output empty;
- output [31:0] q;
-
- wire sub_wire0;
- wire [31:0] sub_wire1;
- wire empty = sub_wire0;
- wire [31:0] q = sub_wire1[31:0];
-
- scfifo scfifo_component (
- .rdreq (rdreq),
- .sclr (sclr),
- .clock (clock),
- .wrreq (wrreq),
- .data (data),
- .empty (sub_wire0),
- .q (sub_wire1)
- // synopsys translate_off
- ,
- .aclr (),
- .almost_empty (),
- .almost_full (),
- .full (),
- .usedw ()
- // synopsys translate_on
- );
- defparam
- scfifo_component.add_ram_output_register = "OFF",
- scfifo_component.intended_device_family = "Cyclone",
- scfifo_component.lpm_numwords = 2048,
- scfifo_component.lpm_showahead = "OFF",
- scfifo_component.lpm_type = "scfifo",
- scfifo_component.lpm_width = 32,
- scfifo_component.lpm_widthu = 11,
- scfifo_component.overflow_checking = "OFF",
- scfifo_component.underflow_checking = "OFF",
- scfifo_component.use_eab = "ON";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "2048"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "32"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_bb.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_waveforms.html FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_wave*.jpg FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v deleted file mode 100644 index 1023d2f25..000000000 --- a/gr-radar-mono/src/fpga/lib/radar.v +++ /dev/null @@ -1,81 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../lib/radar_config.vh" - -module radar(clk_i,saddr_i,sdata_i,s_strobe_i, - tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o, - rx_adc_i_i,rx_adc_q_i, - rx_strobe_o,rx_ech_i_o,rx_ech_q_o,io_tx_ena_o); - - // System interface - input clk_i; // Master clock @ 64 MHz - input [6:0] saddr_i; // Configuration bus address - input [31:0] sdata_i; // Configuration bus data - input s_strobe_i; // Configuration bus write - - // Transmit subsystem - output tx_side_o; // Transmitter slot - output tx_strobe_o; // Generate an transmitter output sample - output [13:0] tx_dac_i_o; // I channel transmitter output to DAC - output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC - output io_tx_ena_o; // Transmit/Receive switching - - // Receive subsystem - input [15:0] rx_adc_i_i; // I channel input from ADC - input [15:0] rx_adc_q_i; // Q channel input from ADC - output rx_strobe_o; // Indicates output samples ready for Rx FIFO - output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO - output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO - - // Application control - wire reset; // Master application reset - wire tx_side; // Transmitter slot - wire debug_enabled; // Enable debugging mode; - wire tx_enable; // Transmitter enable - wire rx_enable; // Receiver enable - wire tx_ctrl; // Transmitter on control - wire rx_ctrl; // Receiver on control - wire [15:0] pulse_num; // Count of pulses since tx_enabled - - // Configuration - wire [15:0] ampl; // Pulse amplitude - wire [31:0] fstart; // Chirp start frequency - wire [31:0] fincr; // Chirp per strobe frequency increment - - radar_control controller - (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i), - .reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled), - .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl), - .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num), - .io_tx_ena_o(io_tx_ena_o)); - - radar_tx transmitter - ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o), - .ampl_i(ampl),.fstart_i(fstart),.fincr_i(fincr), - .tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) ); - - radar_rx receiver - ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled), - .pulse_num_i(pulse_num),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i), - .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) ); - -endmodule // radar diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh deleted file mode 100644 index 89a336735..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_config.vh +++ /dev/null @@ -1,41 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -`define FR_RADAR_MODE `FR_USER_0 -`define bmFR_RADAR_MODE_RESET 32'b1 << 0 -`define bmFR_RADAR_TXSIDE 32'b1 << 1 -`define bmFR_RADAR_LOOP 32'b1 << 2 -`define bmFR_RADAR_META 32'b1 << 3 -`define bmFR_RADAR_DERAMP 32'b1 << 4 -`define bmFR_RADAR_CHIRPS 32'b11 << 5 -`define bmFR_RADAR_DEBUG 32'b1 << 7 - -`define FR_RADAR_TON `FR_USER_1 -`define FR_RADAR_TSW `FR_USER_2 -`define FR_RADAR_TLOOK `FR_USER_3 -`define FR_RADAR_TIDLE `FR_USER_4 -`define FR_RADAR_AMPL `FR_USER_5 -`define FR_RADAR_FSTART `FR_USER_6 -`define FR_RADAR_FINCR `FR_USER_7 -`define FR_RADAR_ATRDEL `FR_USER_8 diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v deleted file mode 100644 index 05b78198d..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_control.v +++ /dev/null @@ -1,166 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../lib/radar_config.vh" - -module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o, - tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o, - ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o); - - // System interface - input clk_i; // Master clock @ 64 MHz - input [6:0] saddr_i; // Configuration bus address - input [31:0] sdata_i; // Configuration bus data - input s_strobe_i; // Configuration bus write - - // Control and configuration outputs - output reset_o; - output tx_side_o; - output dbg_o; - output tx_strobe_o; - output tx_ctrl_o; - output rx_ctrl_o; - output [15:0] ampl_o; - output [31:0] fstart_o; - output [31:0] fincr_o; - output [15:0] pulse_num_o; - output io_tx_ena_o; - - // Internal configuration - wire lp_ena; - wire md_ena; - wire dr_ena; - wire [1:0] chirps; - wire [15:0] t_on; - wire [15:0] t_sw; - wire [15:0] t_look; - wire [31:0] t_idle; - wire [31:0] atrdel; - - // Configuration from host - wire [31:0] mode; - setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(mode)); - assign reset_o = mode[0]; - assign tx_side_o = mode[1]; - assign lp_ena = mode[2]; - assign md_ena = mode[3]; - assign dr_ena = mode[4]; - assign chirps = mode[6:5]; - assign dbg_o = mode[7]; - - setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_on)); - - setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_sw)); - - setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_look)); - - setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(t_idle)); - - setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(ampl_o)); - - setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(fstart_o)); - - setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(fincr_o)); - - setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(atrdel)); - - // Pulse state machine - `define ST_ON 4'b0001 - `define ST_SW 4'b0010 - `define ST_LOOK 4'b0100 - `define ST_IDLE 4'b1000 - - reg [3:0] state; - reg [31:0] count; - reg [15:0] pulse_num_o; - - always @(posedge clk_i) - if (reset_o) - begin - state <= `ST_ON; - count <= 32'b0; - pulse_num_o <= 16'b0; - end - else - case (state) - `ST_ON: - if (count == {16'b0,t_on}) - begin - state <= `ST_SW; - count <= 32'b0; - pulse_num_o <= pulse_num_o + 16'b1; - end - else - count <= count + 32'b1; - - `ST_SW: - if (count == {16'b0,t_sw}) - begin - state <= `ST_LOOK; - count <= 32'b0; - end - else - count <= count + 32'b1; - - `ST_LOOK: - if (count == {16'b0,t_look}) - begin - state <= `ST_IDLE; - count <= 32'b0; - end - else - count <= count + 32'b1; - - `ST_IDLE: - if (count == t_idle) - begin - state <= `ST_ON; - count <= 32'b0; - end - else - count <= count + 32'b1; - - default: // Invalid state, reset state machine - begin - state <= `ST_ON; - count <= 32'b0; - end - endcase - - assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz - assign tx_ctrl_o = (state == `ST_ON); - assign rx_ctrl_o = (state == `ST_LOOK); - - // Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch - atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o), - .tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]), - .atr_tx_o(io_tx_ena_o)); - -endmodule // radar_control diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v deleted file mode 100644 index 4b0b83c49..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_rx.v +++ /dev/null @@ -1,109 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i, - rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o); - - input clk_i; - input rst_i; - input ena_i; - input dbg_i; - - input [15:0] rx_in_i_i; - input [15:0] rx_in_q_i; - input [15:0] pulse_num_i; - - output [15:0] rx_i_o; - output [15:0] rx_q_o; - output reg rx_strobe_o; - - reg [15:0] count; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - count <= 16'b0; - else - count <= count + 16'b1; - - wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i}; - - // Buffer incoming samples every clock - wire [31:0] fifo_out; - reg fifo_ack; - wire fifo_empty; - -// Use model if simulating, otherwise Altera Megacell -`ifdef SIMULATION - fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i), - .data(fifo_inp),.wrreq(ena_i), - .rdreq(fifo_ack),.q(fifo_out), - .empty(fifo_empty)); -`else - fifo32_2k buffer(.clock(clk_i),.sclr(rst_i), - .data(fifo_inp),.wrreq(ena_i), - .rdreq(fifo_ack),.q(fifo_out), - .empty(fifo_empty)); -`endif - - // Write samples to rx_fifo every third clock - `define ST_FIFO_IDLE 3'b001 - `define ST_FIFO_STROBE 3'b010 - `define ST_FIFO_ACK 3'b100 - - reg [2:0] state; - - always @(posedge clk_i) - if (rst_i) - begin - state <= `ST_FIFO_IDLE; - rx_strobe_o <= 1'b0; - fifo_ack <= 1'b0; - end - else - case (state) - `ST_FIFO_IDLE: - if (!fifo_empty) - begin - // Tell rx_fifo sample is ready - rx_strobe_o <= 1'b1; - state <= `ST_FIFO_STROBE; - end - `ST_FIFO_STROBE: - begin - rx_strobe_o <= 1'b0; - // Ack our FIFO - fifo_ack <= 1'b1; - state <= `ST_FIFO_ACK; - end - `ST_FIFO_ACK: - begin - fifo_ack <= 1'b0; - state <= `ST_FIFO_IDLE; - end - endcase // case(state) - - assign rx_i_o = fifo_out[31:16]; - assign rx_q_o = fifo_out[15:0]; - -endmodule // radar_rx diff --git a/gr-radar-mono/src/fpga/lib/radar_tx.v b/gr-radar-mono/src/fpga/lib/radar_tx.v deleted file mode 100644 index c20dd0c1a..000000000 --- a/gr-radar-mono/src/fpga/lib/radar_tx.v +++ /dev/null @@ -1,59 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module radar_tx(clk_i,rst_i,ena_i,strobe_i, - ampl_i,fstart_i,fincr_i, - tx_i_o,tx_q_o); - - // System control - input clk_i; - input rst_i; - input ena_i; - input strobe_i; - - // Configuration - input [15:0] ampl_i; - input [31:0] fstart_i; - input [31:0] fincr_i; - - // Chirp output - output [13:0] tx_i_o; - output [13:0] tx_q_o; - wire [15:0] cordic_i, cordic_q; - - // Chirp generator - reg [31:0] freq; - - always @(posedge clk_i) - if (rst_i | ~ena_i) - freq <= fstart_i; - else - if (strobe_i) - freq <= freq + fincr_i; - - cordic_nco nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i), - .ampl_i(ampl_i),.freq_i(freq),.phs_i(0), - .data_i_o(cordic_i),.data_q_o(cordic_q)); - - assign tx_i_o = cordic_i[13:0]; - assign tx_q_o = cordic_q[13:0]; - -endmodule // radar_tx diff --git a/gr-radar-mono/src/fpga/models/.gitignore b/gr-radar-mono/src/fpga/models/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/fpga/models/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/models/Makefile.am b/gr-radar-mono/src/fpga/models/Makefile.am deleted file mode 100644 index 8a1a09597..000000000 --- a/gr-radar-mono/src/fpga/models/Makefile.am +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - fifo_1clk.v diff --git a/gr-radar-mono/src/fpga/models/fifo_1clk.v b/gr-radar-mono/src/fpga/models/fifo_1clk.v deleted file mode 100644 index 93ada6c8d..000000000 --- a/gr-radar-mono/src/fpga/models/fifo_1clk.v +++ /dev/null @@ -1,88 +0,0 @@ -/* -*- verilog -*- */ -/* - * Copyright (C) 2003 Matt Ettus - * Copyright (C) 2007 Corgan Enterprises LLC - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -// Model of Altera FIFO with common clock domain - -module fifo_1clk(data, wrreq, rdreq, clock, sclr, q, - full, empty, usedw); - - parameter width = 32; - parameter depth = 4096; - //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req - - input [31:0] data; - input wrreq; - input rdreq; - input clock; - input sclr; - output [31:0] q; - output full; - output empty; - output [11:0] usedw; - - reg [width-1:0] mem [0:depth-1]; - reg [7:0] rdptr; - reg [7:0] wrptr; - -`ifdef rd_req - reg [width-1:0] q; -`else - wire [width-1:0] q; -`endif - - reg [11:0] usedw; - - integer i; - - always @( sclr) - begin - wrptr <= #1 0; - rdptr <= #1 0; - for(i=0;i<depth;i=i+1) - mem[i] <= #1 0; - end - - always @(posedge clock) - if(wrreq) - begin - wrptr <= #1 wrptr+1; - mem[wrptr] <= #1 data; - end - - always @(posedge clock) - if(rdreq) - begin - rdptr <= #1 rdptr+1; -`ifdef rd_req - q <= #1 mem[rdptr]; -`endif - end - -`ifdef rd_req -`else - assign q = mem[rdptr]; -`endif - - always @(posedge clock) - usedw <= #1 wrptr - rdptr; - - assign empty = (wrptr == rdptr); -endmodule diff --git a/gr-radar-mono/src/fpga/tb/.gitignore b/gr-radar-mono/src/fpga/tb/.gitignore deleted file mode 100644 index d709d8c29..000000000 --- a/gr-radar-mono/src/fpga/tb/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -/Makefile -/Makefile.in -/radar_tb -/out -/*.out* -/*.vcd diff --git a/gr-radar-mono/src/fpga/tb/Makefile.am b/gr-radar-mono/src/fpga/tb/Makefile.am deleted file mode 100644 index da45f497a..000000000 --- a/gr-radar-mono/src/fpga/tb/Makefile.am +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -EXTRA_DIST += \ - radar_tb.v \ - radar_tb.sav \ - radar_tb.sh \ - radar_tb_wave.sh - -MOSTLYCLEANFILES += *.vcd *.out* radar_tb diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.sav b/gr-radar-mono/src/fpga/tb/radar_tb.sav deleted file mode 100644 index 66289c07e..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb.sav +++ /dev/null @@ -1,42 +0,0 @@ -*-24.712532 40200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -radar_tb.clk -radar_tb.ena -radar_tb.rst -radar_tb.uut.reset -@200 -- -@420 -radar_tb.uut.controller.ampl_o[15:0] -@22 -radar_tb.uut.controller.fstart_o[31:0] -radar_tb.uut.controller.fincr_o[31:0] -radar_tb.uut.transmitter.freq[31:0] -@200 -- -@28 -radar_tb.tx_strobe -@8420 -radar_tb.uut.tx_dac_i_o[13:0] -@8421 -radar_tb.uut.tx_dac_q_o[13:0] -@200 -- -@28 -radar_tb.uut.io_tx_ena_o -radar_tb.uut.controller.tx_ctrl_o -radar_tb.uut.controller.rx_ctrl_o -@200 -- -@28 -radar_tb.fifo_strobe -@8024 -radar_tb.fifo_i[15:0] -@22 -radar_tb.fifo_q[15:0] -@200 -- -@22 -radar_tb.uut.pulse_num[15:0] -@200 -- diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.sh b/gr-radar-mono/src/fpga/tb/radar_tb.sh deleted file mode 100755 index dabbe6754..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh -iverilog \ - -D SIMULATION \ - -y ../lib/ \ - -y ../../../../usrp/fpga/sdr_lib \ - -y ../models/ \ - radar_tb.v -o radar_tb && ./radar_tb > radar_tb.out diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.v b/gr-radar-mono/src/fpga/tb/radar_tb.v deleted file mode 100644 index 3583b70e9..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb.v +++ /dev/null @@ -1,215 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`timescale 1ns/1ps - -`include "../lib/radar.v" - -module radar_tb; - - // System bus - reg clk; - reg rst; - reg ena; - - // Configuration bus - reg [6:0] saddr; - reg [31:0] sdata; - reg s_strobe; - - // DAC bus - wire tx_strobe; - wire [13:0] tx_dac_i; - wire [13:0] tx_dac_q; - - // ADC bus - reg [15:0] rx_adc_i; - reg [15:0] rx_adc_q; - - // FIFO bus - wire fifo_strobe; - wire [15:0] fifo_i; - wire [15:0] fifo_q; - - // Configuration shadow registers - reg [31:0] mode; - - radar uut - (.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe), - .tx_strobe_o(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q), - .rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q), - .rx_strobe_o(fifo_strobe),.rx_ech_i_o(fifo_i),.rx_ech_q_o(fifo_q)); - - // Start up initialization - initial - begin - clk = 0; - rst = 0; - ena = 0; - saddr = 0; - sdata = 0; - s_strobe = 0; - rx_adc_i = 0; - rx_adc_q = 0; - mode = 0; - - @(posedge clk); - rst = 1; - @(posedge clk); - rst = 0; - @(posedge clk); - ena = 1; - end - - always - #5 clk <= ~clk; - - initial - begin - //$monitor($time, " clk=%b rst=%b", clk, uut.reset); - - $dumpfile("radar_tb.vcd"); - $dumpvars(0, radar_tb); - end - - // Test tasks - task write_cfg_register; - input [6:0] regno; - input [31:0] value; - - begin - @(posedge clk); - saddr <= regno; - sdata <= value; - s_strobe <= 1'b1; - @(posedge clk); - s_strobe <= 0; - end - endtask // write_cfg_register - - // Application reset line - task set_reset; - input reset; - - begin - mode = reset ? (mode | `bmFR_RADAR_MODE_RESET) : (mode & ~`bmFR_RADAR_MODE_RESET); - write_cfg_register(`FR_RADAR_MODE, mode); - end - endtask // reset - - // Waveform on time - task set_ton; - input [23:0] t_on; - - begin - write_cfg_register(`FR_RADAR_TON, t_on); - end - endtask // set_ton - - // Transmitter switching time - task set_tsw; - input [23:0] t_sw; - - begin - write_cfg_register(`FR_RADAR_TSW, t_sw); - end - endtask // t_sw - - // Receiver look time - task set_tlook; - input [23:0] t_look; - - begin - write_cfg_register(`FR_RADAR_TLOOK, t_look); - end - endtask // set_tlook - - // Inter-pulse idle time - task set_tidle; - input [23:0] t_idle; - - begin - write_cfg_register(`FR_RADAR_TIDLE, t_idle); - end - endtask // set_tidle - - // Chirp amplitude - task set_ampl; - input [31:0] ampl; - - begin - write_cfg_register(`FR_RADAR_AMPL, ampl); - end - endtask // set_ampl - - // Chirp start frequency - task set_fstart; - input [31:0] fstart; - - begin - write_cfg_register(`FR_RADAR_FSTART, fstart); - end - endtask // set_fstart - - // Chirp frequency increment - task set_fincr; - input [31:0] fincr; - - begin - write_cfg_register(`FR_RADAR_FINCR, fincr); - end - endtask // set_fincr - - // Chirp frequency increment - task set_atrdel; - input [31:0] atrdel; - - begin - write_cfg_register(`FR_RADAR_ATRDEL, atrdel); - end - endtask // set_fincr - - // Test transmitter functionality - task test_tx; - begin - #20 set_reset(1); - - #20 set_ton(320-1); // 5us on time - #20 set_tsw(26-1); // 406ns switching time - #20 set_tlook(640-1); // 10us look time - #20 set_tidle(2854-1); // 60us pulse period - - #20 set_ampl(16'd9946); - #20 set_fstart(32'h80000000); // -16 to 16 MHz - #20 set_fincr (32'h0199999A); - #20 set_atrdel(32'h00400046); // 64 TX clks, 70 RX clks - #20 set_reset(0); - #200000; - end - endtask // test_tx - - // Execute tests - initial - begin - #20 test_tx; - #100 $finish; - end -endmodule diff --git a/gr-radar-mono/src/fpga/tb/radar_tb_wave.sh b/gr-radar-mono/src/fpga/tb/radar_tb_wave.sh deleted file mode 100755 index 45bba9f5e..000000000 --- a/gr-radar-mono/src/fpga/tb/radar_tb_wave.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -gtkwave radar_tb.vcd radar_tb.sav diff --git a/gr-radar-mono/src/fpga/top/.gitignore b/gr-radar-mono/src/fpga/top/.gitignore deleted file mode 100644 index 40492321d..000000000 --- a/gr-radar-mono/src/fpga/top/.gitignore +++ /dev/null @@ -1,21 +0,0 @@ -/*.qmsg -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.rbf -/*.smsg -/*.sof -/*.ttf -/*.summary -/undo_redo.txt -/db -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/fpga/top/Makefile.am b/gr-radar-mono/src/fpga/top/Makefile.am deleted file mode 100644 index 51f73ebfe..000000000 --- a/gr-radar-mono/src/fpga/top/Makefile.am +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -RBFS = usrp_radar_mono.rbf - -rbf2datadir = $(prefix)/share/usrp/rev2 -dist_rbf2data_DATA = $(RBFS) - -rbf4datadir = $(prefix)/share/usrp/rev4 -dist_rbf4data_DATA = $(RBFS) - -EXTRA_DIST += \ - usrp_radar_mono.csf \ - usrp_radar_mono.esf \ - usrp_radar_mono.psf \ - usrp_radar_mono.qpf \ - usrp_radar_mono.qsf \ - usrp_radar_mono.v - -MOSTLYCLEANFILES += \ - db/* \ - *.rpt \ - *.summary \ - *.qws \ - *.smsg \ - *.done \ - *.pin \ - *.sof diff --git a/gr-radar-mono/src/fpga/top/config.vh b/gr-radar-mono/src/fpga/top/config.vh deleted file mode 100644 index 176979412..000000000 --- a/gr-radar-mono/src/fpga/top/config.vh +++ /dev/null @@ -1,24 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Uncomment to enable 64 MHz Tx clock, otherwise 32 MHz -//`define TX_RATE_MAX - diff --git a/gr-radar-mono/src/fpga/top/dacpll.v b/gr-radar-mono/src/fpga/top/dacpll.v deleted file mode 100644 index f3941bc67..000000000 --- a/gr-radar-mono/src/fpga/top/dacpll.v +++ /dev/null @@ -1,291 +0,0 @@ -// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: dacpll.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 7.0 Build 33 02/05/2007 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2007 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module dacpll (
- areset,
- inclk0,
- c0);
-
- input areset;
- input inclk0;
- output c0;
-
- wire [5:0] sub_wire0;
- wire [0:0] sub_wire4 = 1'h0;
- wire [0:0] sub_wire1 = sub_wire0[0:0];
- wire c0 = sub_wire1;
- wire sub_wire2 = inclk0;
- wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
-
- altpll altpll_component (
- .inclk (sub_wire3),
- .areset (areset),
- .clk (sub_wire0),
- .activeclock (),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b1),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbout (),
- .locked (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.clk0_divide_by = 1,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 2,
- altpll_component.clk0_phase_shift = "0000",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.inclk0_input_frequency = 15625,
- altpll_component.intended_device_family = "Cyclone",
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.pll_type = "AUTO",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_USED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_UNUSED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_UNUSED",
- altpll_component.port_clk3 = "PORT_UNUSED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf deleted file mode 100644 index 121b15aaf..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |usrp_radar_mono; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(usrp_radar_mono) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf deleted file mode 100644 index 6a8aaae42..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = usrp_radar_mono; -} diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf deleted file mode 100644 index 064967399..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(usrp_radar_mono) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"; -} -THIRD_PARTY_EDA_TOOLS(usrp_radar_mono) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>"; - EDA_SIMULATION_TOOL = "<NONE>"; - EDA_TIMING_ANALYSIS_TOOL = "<NONE>"; - EDA_BOARD_DESIGN_TOOL = "<NONE>"; - EDA_FORMAL_VERIFICATION_TOOL = "<NONE>"; - EDA_RESYNTHESIS_TOOL = "<NONE>"; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf deleted file mode 100644 index d85239e99..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "usrp_radar_mono" diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf deleted file mode 100644 index 9b13989c2..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf +++ /dev/null @@ -1,402 +0,0 @@ -# Copyright (C) 1991-2007 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# usrp_radar_mono_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1" -set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf - -# Pin & Location Assignments -# ========================== -set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -set_location_assignment PIN_29 -to SCLK -set_location_assignment PIN_117 -to SDI -set_location_assignment PIN_28 -to usbclk -set_location_assignment PIN_107 -to usbctl[0] -set_location_assignment PIN_106 -to usbctl[1] -set_location_assignment PIN_105 -to usbctl[2] -set_location_assignment PIN_100 -to usbdata[0] -set_location_assignment PIN_84 -to usbdata[10] -set_location_assignment PIN_83 -to usbdata[11] -set_location_assignment PIN_82 -to usbdata[12] -set_location_assignment PIN_79 -to usbdata[13] -set_location_assignment PIN_78 -to usbdata[14] -set_location_assignment PIN_77 -to usbdata[15] -set_location_assignment PIN_99 -to usbdata[1] -set_location_assignment PIN_98 -to usbdata[2] -set_location_assignment PIN_95 -to usbdata[3] -set_location_assignment PIN_94 -to usbdata[4] -set_location_assignment PIN_93 -to usbdata[5] -set_location_assignment PIN_88 -to usbdata[6] -set_location_assignment PIN_87 -to usbdata[7] -set_location_assignment PIN_86 -to usbdata[8] -set_location_assignment PIN_85 -to usbdata[9] -set_location_assignment PIN_104 -to usbrdy[0] -set_location_assignment PIN_101 -to usbrdy[1] -set_location_assignment PIN_76 -to FX2_1 -set_location_assignment PIN_75 -to FX2_2 -set_location_assignment PIN_74 -to FX2_3 -set_location_assignment PIN_116 -to io_rx_a[0] -set_location_assignment PIN_115 -to io_rx_a[1] -set_location_assignment PIN_114 -to io_rx_a[2] -set_location_assignment PIN_113 -to io_rx_a[3] -set_location_assignment PIN_108 -to io_rx_a[4] -set_location_assignment PIN_195 -to io_rx_a[5] -set_location_assignment PIN_196 -to io_rx_a[6] -set_location_assignment PIN_197 -to io_rx_a[7] -set_location_assignment PIN_200 -to io_rx_a[8] -set_location_assignment PIN_201 -to io_rx_a[9] -set_location_assignment PIN_202 -to io_rx_a[10] -set_location_assignment PIN_203 -to io_rx_a[11] -set_location_assignment PIN_206 -to io_rx_a[12] -set_location_assignment PIN_207 -to io_rx_a[13] -set_location_assignment PIN_208 -to io_rx_a[14] -set_location_assignment PIN_214 -to io_rx_b[0] -set_location_assignment PIN_215 -to io_rx_b[1] -set_location_assignment PIN_216 -to io_rx_b[2] -set_location_assignment PIN_217 -to io_rx_b[3] -set_location_assignment PIN_218 -to io_rx_b[4] -set_location_assignment PIN_219 -to io_rx_b[5] -set_location_assignment PIN_222 -to io_rx_b[6] -set_location_assignment PIN_223 -to io_rx_b[7] -set_location_assignment PIN_224 -to io_rx_b[8] -set_location_assignment PIN_225 -to io_rx_b[9] -set_location_assignment PIN_226 -to io_rx_b[10] -set_location_assignment PIN_227 -to io_rx_b[11] -set_location_assignment PIN_228 -to io_rx_b[12] -set_location_assignment PIN_233 -to io_rx_b[13] -set_location_assignment PIN_234 -to io_rx_b[14] -set_location_assignment PIN_175 -to io_tx_a[0] -set_location_assignment PIN_176 -to io_tx_a[1] -set_location_assignment PIN_177 -to io_tx_a[2] -set_location_assignment PIN_178 -to io_tx_a[3] -set_location_assignment PIN_179 -to io_tx_a[4] -set_location_assignment PIN_180 -to io_tx_a[5] -set_location_assignment PIN_181 -to io_tx_a[6] -set_location_assignment PIN_182 -to io_tx_a[7] -set_location_assignment PIN_183 -to io_tx_a[8] -set_location_assignment PIN_184 -to io_tx_a[9] -set_location_assignment PIN_185 -to io_tx_a[10] -set_location_assignment PIN_186 -to io_tx_a[11] -set_location_assignment PIN_187 -to io_tx_a[12] -set_location_assignment PIN_188 -to io_tx_a[13] -set_location_assignment PIN_193 -to io_tx_a[14] -set_location_assignment PIN_73 -to io_tx_b[0] -set_location_assignment PIN_68 -to io_tx_b[1] -set_location_assignment PIN_67 -to io_tx_b[2] -set_location_assignment PIN_66 -to io_tx_b[3] -set_location_assignment PIN_65 -to io_tx_b[4] -set_location_assignment PIN_64 -to io_tx_b[5] -set_location_assignment PIN_63 -to io_tx_b[6] -set_location_assignment PIN_62 -to io_tx_b[7] -set_location_assignment PIN_61 -to io_tx_b[8] -set_location_assignment PIN_60 -to io_tx_b[9] -set_location_assignment PIN_59 -to io_tx_b[10] -set_location_assignment PIN_58 -to io_tx_b[11] -set_location_assignment PIN_57 -to io_tx_b[12] -set_location_assignment PIN_56 -to io_tx_b[13] -set_location_assignment PIN_55 -to io_tx_b[14] -set_location_assignment PIN_152 -to master_clk -set_location_assignment PIN_144 -to rx_a_a[0] -set_location_assignment PIN_143 -to rx_a_a[1] -set_location_assignment PIN_141 -to rx_a_a[2] -set_location_assignment PIN_140 -to rx_a_a[3] -set_location_assignment PIN_139 -to rx_a_a[4] -set_location_assignment PIN_138 -to rx_a_a[5] -set_location_assignment PIN_137 -to rx_a_a[6] -set_location_assignment PIN_136 -to rx_a_a[7] -set_location_assignment PIN_135 -to rx_a_a[8] -set_location_assignment PIN_134 -to rx_a_a[9] -set_location_assignment PIN_133 -to rx_a_a[10] -set_location_assignment PIN_132 -to rx_a_a[11] -set_location_assignment PIN_23 -to rx_a_b[0] -set_location_assignment PIN_21 -to rx_a_b[1] -set_location_assignment PIN_20 -to rx_a_b[2] -set_location_assignment PIN_19 -to rx_a_b[3] -set_location_assignment PIN_18 -to rx_a_b[4] -set_location_assignment PIN_17 -to rx_a_b[5] -set_location_assignment PIN_16 -to rx_a_b[6] -set_location_assignment PIN_15 -to rx_a_b[7] -set_location_assignment PIN_14 -to rx_a_b[8] -set_location_assignment PIN_13 -to rx_a_b[9] -set_location_assignment PIN_12 -to rx_a_b[10] -set_location_assignment PIN_11 -to rx_a_b[11] -set_location_assignment PIN_131 -to rx_b_a[0] -set_location_assignment PIN_128 -to rx_b_a[1] -set_location_assignment PIN_127 -to rx_b_a[2] -set_location_assignment PIN_126 -to rx_b_a[3] -set_location_assignment PIN_125 -to rx_b_a[4] -set_location_assignment PIN_124 -to rx_b_a[5] -set_location_assignment PIN_123 -to rx_b_a[6] -set_location_assignment PIN_122 -to rx_b_a[7] -set_location_assignment PIN_121 -to rx_b_a[8] -set_location_assignment PIN_120 -to rx_b_a[9] -set_location_assignment PIN_119 -to rx_b_a[10] -set_location_assignment PIN_118 -to rx_b_a[11] -set_location_assignment PIN_8 -to rx_b_b[0] -set_location_assignment PIN_7 -to rx_b_b[1] -set_location_assignment PIN_6 -to rx_b_b[2] -set_location_assignment PIN_5 -to rx_b_b[3] -set_location_assignment PIN_4 -to rx_b_b[4] -set_location_assignment PIN_3 -to rx_b_b[5] -set_location_assignment PIN_2 -to rx_b_b[6] -set_location_assignment PIN_240 -to rx_b_b[7] -set_location_assignment PIN_239 -to rx_b_b[8] -set_location_assignment PIN_238 -to rx_b_b[9] -set_location_assignment PIN_237 -to rx_b_b[10] -set_location_assignment PIN_236 -to rx_b_b[11] -set_location_assignment PIN_156 -to SDO -set_location_assignment PIN_153 -to SEN_FPGA -set_location_assignment PIN_159 -to tx_a[0] -set_location_assignment PIN_160 -to tx_a[1] -set_location_assignment PIN_161 -to tx_a[2] -set_location_assignment PIN_162 -to tx_a[3] -set_location_assignment PIN_163 -to tx_a[4] -set_location_assignment PIN_164 -to tx_a[5] -set_location_assignment PIN_165 -to tx_a[6] -set_location_assignment PIN_166 -to tx_a[7] -set_location_assignment PIN_167 -to tx_a[8] -set_location_assignment PIN_168 -to tx_a[9] -set_location_assignment PIN_169 -to tx_a[10] -set_location_assignment PIN_170 -to tx_a[11] -set_location_assignment PIN_173 -to tx_a[12] -set_location_assignment PIN_174 -to tx_a[13] -set_location_assignment PIN_38 -to tx_b[0] -set_location_assignment PIN_39 -to tx_b[1] -set_location_assignment PIN_41 -to tx_b[2] -set_location_assignment PIN_42 -to tx_b[3] -set_location_assignment PIN_43 -to tx_b[4] -set_location_assignment PIN_44 -to tx_b[5] -set_location_assignment PIN_45 -to tx_b[6] -set_location_assignment PIN_46 -to tx_b[7] -set_location_assignment PIN_47 -to tx_b[8] -set_location_assignment PIN_48 -to tx_b[9] -set_location_assignment PIN_49 -to tx_b[10] -set_location_assignment PIN_50 -to tx_b[11] -set_location_assignment PIN_53 -to tx_b[12] -set_location_assignment PIN_54 -to tx_b[13] -set_location_assignment PIN_158 -to TXSYNC_A -set_location_assignment PIN_37 -to TXSYNC_B -set_location_assignment PIN_235 -to io_rx_b[15] -set_location_assignment PIN_24 -to io_tx_b[15] -set_location_assignment PIN_213 -to io_rx_a[15] -set_location_assignment PIN_194 -to io_tx_a[15] -set_location_assignment PIN_1 -to MYSTERY_SIGNAL - -# Classic Timing Assignments -# ========================== -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -set_global_assignment -name MAX_SCC_SIZE 50 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>" -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON -set_global_assignment -name TOP_LEVEL_ENTITY usrp_radar_mono - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name INC_PLC_MODE OFF -set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF -set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "<None>" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" -set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF - -# Simulator Assignments -# ===================== -set_global_assignment -name START_TIME "0 ns" -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE - -# Design Assistant Assignments -# ============================ -set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF -set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF -set_global_assignment -name ASSG_CAT OFF -set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF -set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF -set_global_assignment -name CLK_CAT OFF -set_global_assignment -name CLK_RULE_COMB_CLOCK OFF -set_global_assignment -name CLK_RULE_INV_CLOCK OFF -set_global_assignment -name CLK_RULE_GATING_SCHEME OFF -set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF -set_global_assignment -name CLK_RULE_MIX_EDGES OFF -set_global_assignment -name RESET_CAT OFF -set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name TIMING_CAT OFF -set_global_assignment -name TIMING_RULE_SHIFT_REG OFF -set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF -set_global_assignment -name NONSYNCHSTRUCT_CAT OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF -set_global_assignment -name SIGNALRACE_CAT OFF -set_global_assignment -name ACLK_CAT OFF -set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF -set_global_assignment -name HCPY_CAT OFF -set_global_assignment -name HCPY_VREF_PINS OFF -set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, D101, D102, D103, H102" -set_global_assignment -name DISABLE_DA_RULE H101 - -# SignalTap II Assignments -# ======================== -set_global_assignment -name HUB_ENTITY_NAME SLD_HUB -set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP OFF - -# LogicLock Region Assignments -# ============================ -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF - -# start CLOCK(SCLK) -# ----------------- - - # Classic Timing Assignments - # ========================== -set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK -set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK - -# end CLOCK(SCLK) -# --------------- - -# start CLOCK(master_clk) -# ----------------------- - - # Classic Timing Assignments - # ========================== -set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk -set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk - -# end CLOCK(master_clk) -# --------------------- - -# start CLOCK(usbclk) -# ------------------- - - # Classic Timing Assignments - # ========================== -set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk -set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk - -# end CLOCK(usbclk) -# ----------------- - -# ----------------------------- -# start ENTITY(usrp_radar_mono) - - # Classic Timing Assignments - # ========================== -set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK -set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk -set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== -set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(usrp_radar_mono) -# --------------------------- -set_global_assignment -name VERILOG_FILE usrp_radar_mono.v -set_global_assignment -name VERILOG_FILE dacpll.v -set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v -set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v -set_global_assignment -name VERILOG_FILE ../lib/fifo32_2k.v -set_global_assignment -name VERILOG_FILE ../lib/radar_control.v -set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v -set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v -set_global_assignment -name VERILOG_FILE ../lib/radar.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v -set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf Binary files differdeleted file mode 100644 index ee8859b1b..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf +++ /dev/null diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf deleted file mode 100644 index e5645322b..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf +++ /dev/null @@ -1,65 +0,0 @@ -{ "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/bustri.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
-{ "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/fifo_4k.v 10 10 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/fifo_4k.v, which is not specified as a design file for the current project, but contains definitions for 10 design units and 10 entities in project" { } { } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 133 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 132 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 130 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 129 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_2 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_2\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 128 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 126 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 125 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_1 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_1\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 124 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 122 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_txval_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_txval_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_txval_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 121 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_mask_0 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_mask_0\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_mask_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 120 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_3 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_3\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 98 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_2 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_2\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 97 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_1 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_1\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 96 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ratio clk_div_0 7 8 " "Warning: Port \"ratio\" on the entity instantiation of \"clk_div_0\" is connected to a signal of width 7. The formal width of the signal in the module is 8. Extra bits will be driven by GND." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "clk_div_0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 95 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be driven by GND." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_debugen 4 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_debugen\" is connected to a signal of width 4. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_debugen" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 93 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxbref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxbref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxbref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 91 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txbref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_txbref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txbref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 90 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxaref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxaref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_rxaref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 89 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_txaref 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_txaref\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_txaref" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 88 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is connected to a signal of width 8. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage11\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage10\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage9\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage8 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage8\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage8" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 97 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage7 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage7\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage7" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 96 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage6 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage6\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage6" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 95 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage5 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage5\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage5" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 94 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage4 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage4\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage4" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 93 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage3 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage3\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 92 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage2\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage1\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage0\" is connected to a signal of width 16. The formal width of the signal in the module is 15. Extra bits will be ignored." { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 81 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 75 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 72 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is connected to a signal of width 11. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a signal of width 20. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a signal of width 4. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND " "Warning: Reduced register \"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "MYSTERY_SIGNAL GND " "Warning: Pin \"MYSTERY_SIGNAL\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FX2_3 GND " "Warning: Pin \"FX2_3\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "usbrdy\[0\] GND " "Warning: Pin \"usbrdy\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "usbctl\[0\] " "Warning: No output dependent on input pin \"usbctl\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 48 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info: Pin MYSTERY_SIGNAL has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3 has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin usbrdy\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 79 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 73 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32. Extra bits will be left dangling without any fanout logic." { } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 67 0 0 } } } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58): truncated value with size 32 to match size of target (12)" { } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71): truncated value with size 32 to match size of target (12)" { } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at serial_io.v(48): object \"write_done\" assigned a value but never read" { } { { "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\" with stuck data_in port to stuck value GND" { } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v b/gr-radar-mono/src/fpga/top/usrp_radar_mono.v deleted file mode 100644 index 2620a3288..000000000 --- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v +++ /dev/null @@ -1,213 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003,2004 Matt Ettus -// Copyright (C) 2007 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module usrp_radar_mono -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64; - - // wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_pkt_rdy; - assign usbrdy[0] = 1'b0; // have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = 1'b0; // tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] rx_numchan; - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - // TX - wire tx_sample_strobe; - wire io_tx_ena; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Transmit Side - - wire tx_side; - wire [13:0] tx_i, tx_q; - wire [13:0] tx_dac; - wire tx_sync; - - dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx), - .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q), - .tx_data_o(tx_dac),.tx_sync_o(tx_sync)); - - // Route transmitted signal to side A or side B - assign tx_a = tx_side ? 14'b0 : tx_dac; - assign tx_b = tx_side ? tx_dac : 14'b0; - assign TXSYNC_A = tx_side ? 1'b0 : tx_sync; - assign TXSYNC_B = tx_side ? tx_sync : 1'b0; - - ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Receive Side - wire rx_strobe; - wire [15:0] rx_adc0_i, rx_adc0_q; - wire [15:0] rx_buf_i, rx_buf_q; - - adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), - .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(), - .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q), - .ddc1_in_i(),.ddc1_in_q(), - .ddc2_in_i(),.ddc2_in_q(), - .ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) ); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .reset_regs(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(rx_buf_i),.ch_1(rx_buf_q), - .ch_2(),.ch_3(), - .ch_4(),.ch_5(), - .ch_6(),.ch_7(), - .rxclk(clk64),.rxstrobe(rx_strobe), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus() ); - - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Top level application - radar radar_mono ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe), - .tx_side_o(tx_side),.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q), - .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q), - .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q),.io_tx_ena_o(io_tx_ena) - ); - - // Route TX enable out to RFX transmit mixer enable - assign io_tx_a[5] = tx_side ? 1'bz : io_tx_ena; - assign io_tx_b[5] = tx_side ? io_tx_ena : 1'bz; - - // Route opposite of TX enable out to RFX receive mixer - //assign io_rx_a[5] = tx_side ? 1'bz : ~io_tx_ena; - //assign io_rx_b[5] = tx_side ? ~io_tx_ena : 1'bz; - assign io_rx_a[5] = 1'b1; - assign io_rx_b[5] = 1'b1; - - - // Route TX enable out to RX/TX switch - assign io_tx_a[6] = tx_side ? 1'bz : ~io_tx_ena; - assign io_tx_b[6] = tx_side ? ~io_tx_ena : 1'bz; - - // Enable common RX/TX antenna - assign io_rx_a[6] = tx_side ? 1'bz : 1'b0; - assign io_rx_b[6] = tx_side ? 1'b0 : 1'bz; - - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities; - assign capabilities[7] = 0; // `TX_CAP_HB; - assign capabilities[6:4] = 1; // `TX_CAP_NCHAN; - assign capabilities[3] = 0; // `RX_CAP_HB; - assign capabilities[2:0] = 2; // `RX_CAP_NCHAN; - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a), - .readback_4(),.readback_5(),.readback_6(),.readback_7() - ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(),.decim_rate(), - .tx_sample_strobe(),.strobe_interp(), - .rx_sample_strobe(),.strobe_decim(), - .tx_empty(), - .debug_0(),.debug_1(), - .debug_2(),.debug_3(), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - wire [1:0] dummy_io = 2'bz; - - io_pins io_pins - (.io_0({io_tx_a[15:7],dummy_io,io_tx_a[4:0]}), // Don't connect pins used above - .io_1({io_rx_a[15:7],dummy_io,io_rx_a[4:0]}), - .io_2({io_tx_b[15:7],dummy_io,io_tx_b[4:0]}), - .io_3({io_rx_b[15:7],dummy_io,io_rx_b[4:0]}), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - -endmodule // usrp_radar_mono diff --git a/gr-radar-mono/src/lib/.gitignore b/gr-radar-mono/src/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-radar-mono/src/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-radar-mono/src/lib/Makefile.am b/gr-radar-mono/src/lib/Makefile.am deleted file mode 100644 index 4f35e3aef..000000000 --- a/gr-radar-mono/src/lib/Makefile.am +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common diff --git a/gr-radar-mono/src/python/.gitignore b/gr-radar-mono/src/python/.gitignore deleted file mode 100644 index f104c5892..000000000 --- a/gr-radar-mono/src/python/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/Makefile -/Makefile.in -/run_tests -/*.pyc diff --git a/gr-radar-mono/src/python/Makefile.am b/gr-radar-mono/src/python/Makefile.am deleted file mode 100644 index 535bb85a4..000000000 --- a/gr-radar-mono/src/python/Makefile.am +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007,2009 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -radar_mono_pythondir = $(grpythondir) - -dist_bin_SCRIPTS = \ - usrp_radar_mono.py - -radar_mono_python_PYTHON = \ - radar_mono.py diff --git a/gr-radar-mono/src/python/qa_nothing.py b/gr-radar-mono/src/python/qa_nothing.py deleted file mode 100644 index e69de29bb..000000000 --- a/gr-radar-mono/src/python/qa_nothing.py +++ /dev/null diff --git a/gr-radar-mono/src/python/radar_mono.py b/gr-radar-mono/src/python/radar_mono.py deleted file mode 100644 index 1a7b9260a..000000000 --- a/gr-radar-mono/src/python/radar_mono.py +++ /dev/null @@ -1,330 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, usrp -from gnuradio import eng_notation -from gr import gr_threading as _threading - -n2s = eng_notation.num_to_str - -txp_delay = 60 # Pipeline delay to turn on transmit mixer -rxp_delay = 76 # Pipeline delay to turn off transmit mixer - -#----------------------------------------------------------------------- -# FPGA Register Definitions -#----------------------------------------------------------------------- -FR_RADAR_MODE = usrp.FR_USER_0 # Operational mode -bmFR_RADAR_MODE_RESET = 1 << 0 # bit 0: active high reset -bmFR_RADAR_TXSIDE = 1 << 1 # bit 1: use TX side A or B -#bmFR_RADAR_MODE_LP = 1 << 2 # bit 2: enable digital loopback -#bmFR_RADAR_MODE_DR = 1 << 3 # bit 3: enable on-board deramping -#bmFR_RADAR_MODE_MD = 1 << 4 # bit 4: enable echo metadata -#bmFR_RADAR_MODE_CHIRPS = 3 << 5 # bit 5,6: number of chirp center frequencies -bmFR_RADAR_DEBUG = 1 << 7 # bit 7: enable debugging mode - -FR_RADAR_TON = usrp.FR_USER_1 # 16-bit transmitter on time in clocks -FR_RADAR_TSW = usrp.FR_USER_2 # 16-bit transmitter switch time in clocks -FR_RADAR_TLOOK = usrp.FR_USER_3 # 16-bit receiver look time in clocks -FR_RADAR_TIDLE = usrp.FR_USER_4 # 32-bit inter-pulse idle time -FR_RADAR_AMPL = usrp.FR_USER_5 # 16-bit pulse amplitude (2s complement) into CORDIC -FR_RADAR_FSTART = usrp.FR_USER_6 # 32-bit FTW for chirp start frequency -FR_RADAR_FINCR = usrp.FR_USER_7 # 32-bit FTW increment per transmit clock -FR_RADAR_ATRDEL = usrp.FR_USER_8 # 16-bit TX delay in clocks, 16-bit RX delay in clocks - -# These are for phase II development (need to renumber) -#FR_RADAR_FREQ1N = usrp.FR_USER_8 # 24-bit N register for chirp #1 -#FR_RADAR_FREQ1R = usrp.FR_USER_9 # 24-bit R register for chirp #1 -#FR_RADAR_FREQ1C = usrp.FR_USER_10 # 24-bit C register for chirp #1 -#FR_RADAR_FREQ2N = usrp.FR_USER_11 # 24-bit N register for chirp #2 -#FR_RADAR_FREQ2R = usrp.FR_USER_12 # 24-bit R register for chirp #2 -#FR_RADAR_FREQ2C = usrp.FR_USER_13 # 24-bit C register for chirp #2 -#FR_RADAR_FREQ3N = usrp.FR_USER_14 # 24-bit N register for chirp #3 -#FR_RADAR_FREQ3R = usrp.FR_USER_15 # 24-bit R register for chirp #3 -#FR_RADAR_FREQ3C = usrp.FR_USER_16 # 24-bit C register for chirp #3 -#FR_RADAR_FREQ4N = usrp.FR_USER_17 # 24-bit N register for chirp #4 -#FR_RADAR_FREQ4R = usrp.FR_USER_18 # 24-bit R register for chirp #4 -#FR_RADAR_FREQ4C = usrp.FR_USER_19 # 24-bit C register for chirp #4 - -#----------------------------------------------------------------------- -# Transmitter object. Uses usrp_sink, but only for a handle to the -# FPGA registers. -#----------------------------------------------------------------------- -class radar_tx(object): - def __init__(self, options): - self._subdev_spec = options.tx_subdev_spec - self._verbose = options.verbose - self._debug = options.debug - self._u = usrp.sink_s(fpga_filename='usrp_radar_mono.rbf') - - if self._subdev_spec == None: - self._subdev_spec = usrp.pick_tx_subdevice(self._u) - - self._subdev = usrp.selected_subdev(self._u, self._subdev_spec) - self._subdev.set_lo_offset(0.0) - self._ton_ticks = 0 - self._tsw_ticks = 0 - self._tlook_ticks = 0 - self._tidle_ticks = 0 - - if self._verbose: - print "Using", self._subdev.name(), "for radar transmitter." - - def set_ton(self, ton): - self._ton_ticks = 2*(int(ton*64e6)/2)-1 # Even number, then subtract 1 - if self._verbose: - print "Setting pulse on time to", ton, " sec ("+`self._ton_ticks+1`+" ticks)" - self._u._write_fpga_reg(FR_RADAR_TON, self._ton_ticks) - - def set_tsw(self, tsw): - self._tsw_ticks = 2*(int(tsw*64e6)/2)-1+rxp_delay # Even number, then subtract 1 - if self._verbose: - print "Setting pulse switching time to", tsw, " sec ("+`self._tsw_ticks+1`+" ticks)" - self._u._write_fpga_reg(FR_RADAR_TSW, self._tsw_ticks) - - def set_tlook(self, tlook): - self._tlook_ticks = 2*(int(tlook*64e6)/2)-1 # Even number, then subtract 1 - if self._verbose: - print "Setting receiver look time to", tlook, " sec ("+`self._tlook_ticks+1`+" ticks)" - self._u._write_fpga_reg(FR_RADAR_TLOOK, self._tlook_ticks) - - def set_prf(self, prf): - period = 2*int(32e6/prf) - self._tidle_ticks = period-(self._ton_ticks+self._tsw_ticks+self._tlook_ticks+3)-1 - if self._verbose: - print "Setting PRF to", prf, "Hz ("+`self._tidle_ticks+1`+" ticks idle time)" - self._u._write_fpga_reg(FR_RADAR_TIDLE, self._tidle_ticks) - - def set_amplitude(self, ampl): - self._amplitude = int(ampl*9946/100.0) # CORDIC gain correction - self._u._write_fpga_reg(FR_RADAR_AMPL, self._amplitude) - - def set_freq(self, center_freq, chirp_width): - self._center_freq = center_freq - self._chirp_width = chirp_width - self._fstart = -int((chirp_width/2)*(2**32)/32e6) - self._fincr = int((chirp_width/16e6)*(2**32)/(self._ton_ticks+1)) - - if self._verbose: - print "Setting transmitter center frequency to", n2s(center_freq) - print "Setting chirp width to", n2s(chirp_width), "Hz "+"("+hex(self._fstart)+", "+hex(self._fincr)+")" - - result = self._u.tune(0, self._subdev, center_freq) - if result == False: - raise RuntimeError("Failed to set transmitter frequency.") - self._u._write_fpga_reg(FR_RADAR_FSTART, self._fstart) - self._u._write_fpga_reg(FR_RADAR_FINCR, self._fincr) - - def start(self): - self._u.start() - self._subdev.set_enable(True) - - def stop(self): - self._subdev.set_enable(False) - self._u.stop() - - def subdev_spec(self): - return self._subdev_spec - - def echo_length(self): - return self._tlook_ticks+1 - - def __del__(self): - del self._subdev # Avoid weak reference error - -#----------------------------------------------------------------------- -# Receiver object. Uses usrp_source_c to receive echo records. -#----------------------------------------------------------------------- -class radar_rx(gr.top_block): - def __init__(self, options, callback): - gr.top_block.__init__(self, "radar_rx") - - self._u = None - self._subdev_spec = options.rx_subdev_spec - self._gain = options.gain - self._verbose = options.verbose - self._debug = options.debug - self._callback = callback - self._length_set = False - self._connected = False - self._frequency = 0.0 - self._msgq = gr.msg_queue() - self._watcher = _queue_watcher_thread(self._msgq, self._callback) - - def set_echo_length(self, length): - # Only call once - if self._length_set is True: - raise RuntimeError("Can only set echo length once.") - self._length = length - self._length_set = True - - def tune(self, frequency): - if self._verbose: - print "Setting receiver frequency to", n2s(frequency) - self._frequency = frequency - if (self._u): - result = self._u.tune(0, self._subdev, frequency) - if result == False: - raise RuntimeError("Failed to set receiver frequency.") - - def set_gain(self, gain): - self._gain = gain - if self._gain == None: - # if no gain was specified, use the mid-point in dB - g = self._subdev.gain_range() - self._gain = float(g[0]+g[1])/2 - self._subdev.set_gain(self._gain) - - def begin(self): - if not self._connected: - self._setup_connections() - - if self._verbose: - print "Starting receiver..." - self.start() - - def end(self): - if self._verbose: - print "Stopping receiver..." - self.stop() - self.wait() - if self._verbose: - print "Receiver stopped." - - def _setup_usrp(self): - self._u = usrp.source_c(fpga_filename='usrp_radar_mono.rbf') - if self._subdev_spec == None: - self._subdev_spec = usrp.pick_rx_subdevice(self._u) - self._u.set_mux(usrp.determine_rx_mux_value(self._u, self._subdev_spec)) - self._subdev = usrp.selected_subdev(self._u, self._subdev_spec) - - if self._verbose: - print "Using", self._subdev.side_and_name(), "for radar receiver." - print "Setting receiver gain to", self._gain - self.set_gain(self._gain) - self.tune(self._frequency) - - def _setup_connections(self): - if not self._length_set: - raise RuntimeError("Echo length not set.") - self._setup_usrp() - self._vblen = gr.sizeof_gr_complex*self._length - self._s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self._length) - self._sink = gr.message_sink(self._vblen, self._msgq, False) - self.connect(self._u, self._s2v, self._sink) - - if self._verbose: - print "Generating echo vectors of length", self._length, \ - "(samples)", self._vblen, "(bytes)" - - self._connected = True - -class radar(object): - def __init__(self, options, callback): - - self._verbose = options.verbose - self._debug = options.debug - - self._mode = 0 - self._trans = radar_tx(options) - self._rcvr = radar_rx(options, callback) - self.set_reset(True) - self.set_tx_board(self._trans.subdev_spec()) - self.set_debug(self._debug) - self.set_atrdel() - - def _write_mode(self): - self._trans._u._write_fpga_reg(FR_RADAR_MODE, self._mode) - - def set_reset(self, value): - if value: - self._mode |= bmFR_RADAR_MODE_RESET - else: - self._mode &= ~bmFR_RADAR_MODE_RESET - self._write_mode() - - def set_tx_board(self, tx_subdev_spec): - if tx_subdev_spec[0] == 1: - self._mode |= bmFR_RADAR_TXSIDE - else: - self._mode &= ~bmFR_RADAR_TXSIDE - self._write_mode() - - def set_debug(self, value): - if value: - self._mode |= bmFR_RADAR_DEBUG - else: - self._mode &= ~bmFR_RADAR_DEBUG - self._write_mode() - - def set_ton(self, ton): - self._trans.set_ton(ton) - - def set_tsw(self, tsw): - self._trans.set_tsw(tsw) - - def set_tlook(self, tlook): - self._trans.set_tlook(tlook) - self._rcvr.set_echo_length(self._trans.echo_length()) - - def set_prf(self, prf): - self._trans.set_prf(prf) - - def set_amplitude(self, ampl): - self._trans.set_amplitude(ampl) - - def set_freq(self, center_freq, chirp_width): - self._trans.set_freq(center_freq, chirp_width) - self._rcvr.tune(center_freq) - - def set_atrdel(self, tx_delay=txp_delay, rx_delay=rxp_delay): - if self._verbose: - print "Setting TX delay of", tx_delay, "clocks, RX delay of", rx_delay - self._trans._u._write_fpga_reg(FR_RADAR_ATRDEL, tx_delay << 16 | rx_delay) - - def start(self): - self.set_reset(False) - self._trans.start() - self._rcvr.begin() - - def stop(self): - self._rcvr.end() - self._trans.stop() - self.set_reset(True) - -#----------------------------------------------------------------------- -# Queue watcher. Dispatches received echos to callback. -#----------------------------------------------------------------------- -class _queue_watcher_thread(_threading.Thread): - def __init__(self, msgq, callback): - _threading.Thread.__init__(self) - self.setDaemon(1) - self._msgq = msgq - self._callback = callback - self._keep_running = True - self.start() - - def run(self): - while self._keep_running == True: - msg = self._msgq.delete_head() - if self._callback: - self._callback(msg.to_string()) - diff --git a/gr-radar-mono/src/python/run_tests.in b/gr-radar-mono/src/python/run_tests.in deleted file mode 100644 index 19b6b895c..000000000 --- a/gr-radar-mono/src/python/run_tests.in +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -# 1st parameter is absolute path to component source directory -# 2nd parameter is absolute path to component build directory -# 3rd parameter is path to Python QA directory - -@top_builddir@/run_tests.sh \ - @abs_top_srcdir@/gr-sar-fe \ - @abs_top_builddir@/gr-sar-fe \ - @srcdir@ diff --git a/gr-radar-mono/src/python/usrp_radar_mono.py b/gr-radar-mono/src/python/usrp_radar_mono.py deleted file mode 100755 index 3f2ad28e2..000000000 --- a/gr-radar-mono/src/python/usrp_radar_mono.py +++ /dev/null @@ -1,96 +0,0 @@ -#!/usr/bin/env python -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr -from gnuradio.radar_mono import radar -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from optparse import OptionParser -import sys, time - -n2s = eng_notation.num_to_str -logfile = None - -def process_echo(echo): - global logfile - if logfile is not None: - logfile.write(echo) - -def main(): - global logfile - parser = OptionParser(option_class=eng_option) - parser.add_option("-T", "--tx-subdev-spec", type="subdev", default=None, - help="use transmitter board side A or B (default is first found)") - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, - help="use receiver board side A or B (default is first found)") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-f", "--frequency", type="eng_float", default=0.0, - help="set transmitter center frequency to FREQ in Hz, default is %default", metavar="FREQ") - parser.add_option("-w", "--chirp-width", type="eng_float", default=32e6, - help="set LFM chirp bandwidth in Hz, default is %default", metavar="FREQ") - parser.add_option("-a", "--amplitude", type="eng_float", default=15, - help="set waveform amplitude in % full scale, default is %default,") - parser.add_option("", "--ton", type="eng_float", default=5e-6, - help="set pulse on period in seconds, default is %default,") - parser.add_option("", "--tsw", type="eng_float", default=0.0, - help="set transmitter switching period in seconds, default is %default,") - parser.add_option("", "--tlook", type="eng_float", default=5e-6, - help="set receiver look time in seconds, default is %default,") - parser.add_option("", "--prf", type="eng_float", default=100, - help="set pulse repetition frequency in Hz, default is %default,") - parser.add_option("-v", "--verbose", action="store_true", default=False, - help="enable verbose output, default is disabled") - parser.add_option("-D", "--debug", action="store_true", default=False, - help="enable debugging output, default is disabled") - parser.add_option("-F", "--filename", default=None, - help="log received echos to file") - - (options, args) = parser.parse_args() - - if len(args) != 0: - parser.print_help() - sys.exit(1) - - if options.filename is not None: - if options.verbose: - print "Logging echo records to file: ", options.filename - logfile = open(options.filename, 'wb') - - r = radar(options, process_echo) - - r.set_ton(options.ton) - r.set_tsw(options.tsw) - r.set_tlook(options.tlook) - r.set_prf(options.prf) - r.set_amplitude(options.amplitude) - r.set_freq(options.frequency, options.chirp_width) - - r.start() - raw_input("Press ENTER to stop.") - r.stop() - - if logfile is not None: - logfile.close() - -if __name__ == "__main__": - main() diff --git a/gr-radar-mono/src/utils/calc_avg.m b/gr-radar-mono/src/utils/calc_avg.m deleted file mode 100644 index b240d245e..000000000 --- a/gr-radar-mono/src/utils/calc_avg.m +++ /dev/null @@ -1,8 +0,0 @@ -function avg = calc_avg(rlen, mintime) - avg = read_avg('echos.dat', rlen); - x = 1:rlen; - x = (x/64e6+mintime)*3e8/2; - plot(x, abs(avg), "^;Amplitude;"); - xlabel("Range (meters)"); - axis([max(x) 0]) -endfunction diff --git a/gr-radar-mono/src/utils/czpad.m b/gr-radar-mono/src/utils/czpad.m deleted file mode 100644 index e2131030d..000000000 --- a/gr-radar-mono/src/utils/czpad.m +++ /dev/null @@ -1,8 +0,0 @@ -# Center and zero pad v to length n -function pad = czpad(v, n) - c = n/2; - l = length(v); - pad(c-l/2+1:c+l/2) = v; - pad(c+l/2+1:n) = 0; -endfunction -
\ No newline at end of file diff --git a/gr-radar-mono/src/utils/echo_image.m b/gr-radar-mono/src/utils/echo_image.m deleted file mode 100644 index 2e066aef5..000000000 --- a/gr-radar-mono/src/utils/echo_image.m +++ /dev/null @@ -1,6 +0,0 @@ -function echo_image(filename, data) - d = abs(data); - d = d-min(min(d)); - d = d/(max(max(d)))*255; - pngwrite(filename, d, d, d, ones(size(d))); -endfunction
\ No newline at end of file diff --git a/gr-radar-mono/src/utils/fftcorr.m b/gr-radar-mono/src/utils/fftcorr.m deleted file mode 100644 index 548988973..000000000 --- a/gr-radar-mono/src/utils/fftcorr.m +++ /dev/null @@ -1,4 +0,0 @@ -# Perform circular correlation via FFT -function corr = fftcorr(v,ref) - corr = ifft(conj(fft(ref)).*fft(v)); -endfunction diff --git a/gr-radar-mono/src/utils/pulse b/gr-radar-mono/src/utils/pulse deleted file mode 100644 index 887558d1e..000000000 --- a/gr-radar-mono/src/utils/pulse +++ /dev/null @@ -1,396 +0,0 @@ -# Created by Octave 2.1.73, Tue Sep 25 14:17:22 2007 EDT <jcorgan@mobile> -# name: __nargin__ -# type: scalar -0 -# name: pulse321 -# type: complex matrix -# rows: 64 -# columns: 1 - (-0.0003662109375,0.9998779296875) - (-0.0003662109375,0.9998779296875) - (0,-0.9996337890625) - (0,-0.9996337890625) - (-0.0010986328125,-0.961181640625) - (-0.0010986328125,-0.961181640625) - (0.0072021484375,0.882568359375) - (0.0072021484375,0.882568359375) - (-0.0279541015625,-0.7666015625) - (-0.0279541015625,-0.7666015625) - (0.0765380859375,0.616943359375) - (0.0765380859375,0.616943359375) - (-0.1688232421875,-0.4447021484375) - (-0.1688232421875,-0.4447021484375) - (0.3212890625,0.26611328125) - (0.3212890625,0.26611328125) - (-0.54638671875,-0.1092529296875) - (-0.54638671875,-0.1092529296875) - (0.843994140625,0.012451171875) - (0.843994140625,0.012451171875) - (0.8046875,-0.019775390625) - (0.8046875,-0.019775390625) - (-0.444580078125,0.1688232421875) - (-0.444580078125,0.1688232421875) - (0.147705078125,-0.477294921875) - (0.147705078125,-0.477294921875) - (-0.0032958984375,0.921142578125) - (-0.0032958984375,0.921142578125) - (0.09228515625,0.5811767578125) - (0.09228515625,0.5811767578125) - (-0.4447021484375,-0.1688232421875) - (-0.4447021484375,-0.1688232421875) - (0.9996337890625,0.000244140625) - (0.9996337890625,0.000244140625) - (0.4127197265625,-0.19140625) - (0.4127197265625,-0.19140625) - (-0.0379638671875,0.728759765625) - (-0.0379638671875,0.728759765625) - (0.09228515625,0.5811767578125) - (0.09228515625,0.5811767578125) - (-0.617919921875,-0.0762939453125) - (-0.617919921875,-0.0762939453125) - (-0.6170654296875,0.0765380859375) - (-0.6170654296875,0.0765380859375) - (0.0621337890625,-0.654296875) - (0.0621337890625,-0.654296875) - (-0.127685546875,-0.511962890625) - (-0.127685546875,-0.511962890625) - (0.843994140625,0.012451171875) - (0.843994140625,0.012451171875) - (0.29296875,-0.293212890625) - (0.29296875,-0.293212890625) - (-0.01953125,-0.8046875) - (-0.01953125,-0.8046875) - (0.654296875,0.0618896484375) - (0.654296875,0.0618896484375) - (0.3505859375,-0.239990234375) - (0.3505859375,-0.239990234375) - (-0.0279541015625,-0.7666015625) - (-0.0279541015625,-0.7666015625) - (0.805419921875,0.01953125) - (0.805419921875,0.01953125) - (0.1688232421875,-0.444580078125) - (0.1688232421875,-0.444580078125) -# name: pulse325 -# type: complex matrix -# rows: 320 -# columns: 1 - (-0.0003662109375,0.9998779296875) - (-0.0003662109375,0.9998779296875) - (0,-0.9996337890625) - (0,-0.9996337890625) - (-0.0010986328125,-0.961181640625) - (-0.0010986328125,-0.961181640625) - (0.0072021484375,0.882568359375) - (0.0072021484375,0.882568359375) - (-0.0279541015625,-0.7666015625) - (-0.0279541015625,-0.7666015625) - (0.0765380859375,0.616943359375) - (0.0765380859375,0.616943359375) - (-0.1688232421875,-0.4447021484375) - (-0.1688232421875,-0.4447021484375) - (0.3212890625,0.26611328125) - (0.3212890625,0.26611328125) - (-0.54638671875,-0.1092529296875) - (-0.54638671875,-0.1092529296875) - (0.843994140625,0.012451171875) - (0.843994140625,0.012451171875) - (0.8046875,-0.019775390625) - (0.8046875,-0.019775390625) - (-0.444580078125,0.1688232421875) - (-0.444580078125,0.1688232421875) - (0.147705078125,-0.477294921875) - (0.147705078125,-0.477294921875) - (-0.0032958984375,0.921142578125) - (-0.0032958984375,0.921142578125) - (0.09228515625,0.5811767578125) - (0.09228515625,0.5811767578125) - (-0.4447021484375,-0.1688232421875) - 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- f = fopen(name, "rb"); - s = zeros(1, vlen); - n = 0; - - while (!feof(f)) - t = fread(f, [2, vlen], "float"); - if (size(t) == [2, vlen]) - n = n+1; - c = t(1,:)+t(2,:)*j; - if (n > 10) - s = s+c; - endif - endif - endwhile - - avg = s/(n-1); - - fclose(f); - -endfunction diff --git a/gr-radar-mono/src/utils/read_avg_sec.m b/gr-radar-mono/src/utils/read_avg_sec.m deleted file mode 100644 index 7aa77675d..000000000 --- a/gr-radar-mono/src/utils/read_avg_sec.m +++ /dev/null @@ -1,25 +0,0 @@ -function avg = read_avg_sec(name, vlen) - - f = fopen(name, "rb"); - s = zeros(1, vlen); - n = 0; - m = 0; - - while (!feof(f)) - t = fread(f, [2, vlen], "float"); - if (size(t) == [2, vlen]) - n = n+1; - c = t(1,:)+t(2,:)*j; - s = s+c; - m = m+1; - if (m == 1000) - avg(n/1000,:) = s/1000; - s = zeros(1, vlen); - m = 0; - endif - endif - endwhile - - fclose(f); - -endfunction diff --git a/gr-radar-mono/src/utils/read_echos.m b/gr-radar-mono/src/utils/read_echos.m deleted file mode 100644 index 3fae47b4e..000000000 --- a/gr-radar-mono/src/utils/read_echos.m +++ /dev/null @@ -1,7 +0,0 @@ -# Read echos from file into array -function echos = read_echos(filename, len, drop) - e = read_complex_binary(filename); - n = length(e)/len-drop; - start = drop*len+1; - echos = reshape(e(start:end), len, n).'; -endfunction |