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-rw-r--r--gr-radar-mono/src/fpga/lib/Makefile.am2
-rwxr-xr-x[-rw-r--r--]gr-radar-mono/src/fpga/lib/fifo32_2k.v (renamed from gr-radar-mono/src/fpga/lib/fifo32_4k.v)30
-rw-r--r--gr-radar-mono/src/fpga/lib/radar.v8
-rw-r--r--gr-radar-mono/src/fpga/lib/radar_config.vh1
-rw-r--r--gr-radar-mono/src/fpga/lib/radar_control.v18
-rw-r--r--gr-radar-mono/src/fpga/lib/radar_rx.v4
6 files changed, 37 insertions, 26 deletions
diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am
index 2a7d6d883..2c5205382 100644
--- a/gr-radar-mono/src/fpga/lib/Makefile.am
+++ b/gr-radar-mono/src/fpga/lib/Makefile.am
@@ -28,7 +28,7 @@ EXTRA_DIST = \
radar_tx.v \
radar_rx.v \
dac_interface.v \
- fifo32_4k.v \
+ fifo32_2k.v \
cordic_nco.v
MOSTLYCLEANFILES = *~ *.bak
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_4k.v b/gr-radar-mono/src/fpga/lib/fifo32_2k.v
index f31d020fd..c045b70e7 100644..100755
--- a/gr-radar-mono/src/fpga/lib/fifo32_4k.v
+++ b/gr-radar-mono/src/fpga/lib/fifo32_2k.v
@@ -4,7 +4,7 @@
// MODULE: scfifo
// ============================================================
-// File Name: fifo32_4k.v
+// File Name: fifo32_2k.v
// Megafunction Name(s):
// scfifo
//
@@ -36,7 +36,7 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
-module fifo32_4k (
+module fifo32_2k (
clock,
data,
rdreq,
@@ -78,11 +78,11 @@ module fifo32_4k (
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone",
- scfifo_component.lpm_numwords = 4096,
+ scfifo_component.lpm_numwords = 2048,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
- scfifo_component.lpm_widthu = 12,
+ scfifo_component.lpm_widthu = 11,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
@@ -99,7 +99,7 @@ endmodule
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
@@ -127,11 +127,11 @@ endmodule
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
@@ -150,12 +150,12 @@ endmodule
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_bb.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_wave*.jpg TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v
index d71d9397c..1023d2f25 100644
--- a/gr-radar-mono/src/fpga/lib/radar.v
+++ b/gr-radar-mono/src/fpga/lib/radar.v
@@ -24,7 +24,7 @@
module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
rx_adc_i_i,rx_adc_q_i,
- rx_strobe_o,rx_ech_i_o,rx_ech_q_o,auto_tr_o);
+ rx_strobe_o,rx_ech_i_o,rx_ech_q_o,io_tx_ena_o);
// System interface
input clk_i; // Master clock @ 64 MHz
@@ -37,7 +37,7 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
output tx_strobe_o; // Generate an transmitter output sample
output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
- output auto_tr_o; // Transmit/Receive switching
+ output io_tx_ena_o; // Transmit/Receive switching
// Receive subsystem
input [15:0] rx_adc_i_i; // I channel input from ADC
@@ -65,8 +65,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
(.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
.reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled),
.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
- .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num));
- assign auto_tr_o = tx_ctrl;
+ .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num),
+ .io_tx_ena_o(io_tx_ena_o));
radar_tx transmitter
( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o),
diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh
index 251b2dba3..89a336735 100644
--- a/gr-radar-mono/src/fpga/lib/radar_config.vh
+++ b/gr-radar-mono/src/fpga/lib/radar_config.vh
@@ -38,3 +38,4 @@
`define FR_RADAR_AMPL `FR_USER_5
`define FR_RADAR_FSTART `FR_USER_6
`define FR_RADAR_FINCR `FR_USER_7
+`define FR_RADAR_ATRDEL `FR_USER_8
diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v
index 864941109..05b78198d 100644
--- a/gr-radar-mono/src/fpga/lib/radar_control.v
+++ b/gr-radar-mono/src/fpga/lib/radar_control.v
@@ -23,8 +23,8 @@
module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
- ampl_o,fstart_o,fincr_o,pulse_num_o);
-
+ ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
+
// System interface
input clk_i; // Master clock @ 64 MHz
input [6:0] saddr_i; // Configuration bus address
@@ -42,7 +42,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
output [31:0] fstart_o;
output [31:0] fincr_o;
output [15:0] pulse_num_o;
-
+ output io_tx_ena_o;
+
// Internal configuration
wire lp_ena;
wire md_ena;
@@ -52,7 +53,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
wire [15:0] t_sw;
wire [15:0] t_look;
wire [31:0] t_idle;
-
+ wire [31:0] atrdel;
+
// Configuration from host
wire [31:0] mode;
setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
@@ -86,6 +88,9 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(fincr_o));
+ setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+ .out(atrdel));
+
// Pulse state machine
`define ST_ON 4'b0001
`define ST_SW 4'b0010
@@ -152,5 +157,10 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
assign tx_ctrl_o = (state == `ST_ON);
assign rx_ctrl_o = (state == `ST_LOOK);
+
+ // Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
+ atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
+ .tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
+ .atr_tx_o(io_tx_ena_o));
endmodule // radar_control
diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v
index 29bbadd4d..4b0b83c49 100644
--- a/gr-radar-mono/src/fpga/lib/radar_rx.v
+++ b/gr-radar-mono/src/fpga/lib/radar_rx.v
@@ -55,12 +55,12 @@ module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i,
// Use model if simulating, otherwise Altera Megacell
`ifdef SIMULATION
- fifo_1clk #(32, 4096) buffer(.clock(clk_i),.sclr(rst_i),
+ fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`else
- fifo32_4k buffer(.clock(clk_i),.sclr(rst_i),
+ fifo32_2k buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
generated by cgit (git 2.34.1) at 2024-12-22 10:57:59 +0000