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-rw-r--r--gr-radar-mono/src/fpga/lib/.gitignore2
-rw-r--r--gr-radar-mono/src/fpga/lib/Makefile.am34
-rw-r--r--gr-radar-mono/src/fpga/lib/cordic_nco.v54
-rw-r--r--gr-radar-mono/src/fpga/lib/dac_interface.v60
-rwxr-xr-xgr-radar-mono/src/fpga/lib/fifo32_2k.v161
-rw-r--r--gr-radar-mono/src/fpga/lib/radar.v81
-rw-r--r--gr-radar-mono/src/fpga/lib/radar_config.vh41
-rw-r--r--gr-radar-mono/src/fpga/lib/radar_control.v166
-rw-r--r--gr-radar-mono/src/fpga/lib/radar_rx.v109
-rw-r--r--gr-radar-mono/src/fpga/lib/radar_tx.v59
10 files changed, 0 insertions, 767 deletions
diff --git a/gr-radar-mono/src/fpga/lib/.gitignore b/gr-radar-mono/src/fpga/lib/.gitignore
deleted file mode 100644
index b336cc7ce..000000000
--- a/gr-radar-mono/src/fpga/lib/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-/Makefile
-/Makefile.in
diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am
deleted file mode 100644
index e97ff1b6a..000000000
--- a/gr-radar-mono/src/fpga/lib/Makefile.am
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# Copyright 2007,2009 Free Software Foundation, Inc.
-#
-# This file is part of GNU Radio
-#
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING. If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-#
-
-include $(top_srcdir)/Makefile.common
-
-EXTRA_DIST += \
- radar.v \
- radar_config.vh \
- radar_control.v \
- radar_tx.v \
- radar_rx.v \
- dac_interface.v \
- fifo32_2k.v \
- cordic_nco.v
-
-MOSTLYCLEANFILES += *.bak
diff --git a/gr-radar-mono/src/fpga/lib/cordic_nco.v b/gr-radar-mono/src/fpga/lib/cordic_nco.v
deleted file mode 100644
index b9858baf8..000000000
--- a/gr-radar-mono/src/fpga/lib/cordic_nco.v
+++ /dev/null
@@ -1,54 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-module cordic_nco(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,phs_i,data_i_o,data_q_o);
- input clk_i;
- input rst_i;
- input ena_i;
- input strobe_i;
-
- input [15:0] ampl_i;
- input [31:0] freq_i;
- input [31:0] phs_i;
-
- output [15:0] data_i_o;
- output [15:0] data_q_o;
-
- reg [31:0] phase_reg;
- wire [31:0] phase = phase_reg + phs_i;
- wire [15:0] ampl;
-
- always @(posedge clk_i)
- begin
- if (rst_i | ~ena_i)
- phase_reg <= 32'b0;
- else if (strobe_i)
- phase_reg <= phase_reg + freq_i;
- end
-
- assign ampl = ena_i ? ampl_i : 16'b0;
-
- cordic tx_cordic
- (.clock(clk_i),.reset(rst_i),.enable(strobe_i),
- .xi(ampl),.yi(16'b0),.zi(phase[31:16]),
- .xo(data_i_o),.yo(data_q_o),.zo());
-
-endmodule // cordic_nco
diff --git a/gr-radar-mono/src/fpga/lib/dac_interface.v b/gr-radar-mono/src/fpga/lib/dac_interface.v
deleted file mode 100644
index 209aebd96..000000000
--- a/gr-radar-mono/src/fpga/lib/dac_interface.v
+++ /dev/null
@@ -1,60 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-`include "../top/config.vh"
-
-module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
- input clk_i;
- input rst_i;
- input ena_i;
- input strobe_i;
-
- input [13:0] tx_i_i;
- input [13:0] tx_q_i;
-
- output [13:0] tx_data_o;
- output tx_sync_o;
-
-`ifdef TX_RATE_MAX
- wire clk128;
- reg clk64_d;
- reg [13:0] tx_data_o;
-
- // Create a 128 MHz clock
- dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
-
- // Register the clk64 clock in the clk128 domain
- always @(posedge clk128)
- clk64_d <= clk_i;
-
- // Register the tx data in the clk128 domain
- always @(posedge clk128)
- tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
-
- assign tx_sync_o = clk64_d;
-
-
-`else // !`ifdef TX_RATE_MAX
- assign tx_data_o = strobe_i ? tx_i_i : tx_q_i;
- assign tx_sync_o = strobe_i;
-`endif // !`ifdef TX_RATE_MAX
-
-endmodule // dac_interface
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_2k.v b/gr-radar-mono/src/fpga/lib/fifo32_2k.v
deleted file mode 100755
index c045b70e7..000000000
--- a/gr-radar-mono/src/fpga/lib/fifo32_2k.v
+++ /dev/null
@@ -1,161 +0,0 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: scfifo
-
-// ============================================================
-// File Name: fifo32_2k.v
-// Megafunction Name(s):
-// scfifo
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2007 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module fifo32_2k (
- clock,
- data,
- rdreq,
- sclr,
- wrreq,
- empty,
- q);
-
- input clock;
- input [31:0] data;
- input rdreq;
- input sclr;
- input wrreq;
- output empty;
- output [31:0] q;
-
- wire sub_wire0;
- wire [31:0] sub_wire1;
- wire empty = sub_wire0;
- wire [31:0] q = sub_wire1[31:0];
-
- scfifo scfifo_component (
- .rdreq (rdreq),
- .sclr (sclr),
- .clock (clock),
- .wrreq (wrreq),
- .data (data),
- .empty (sub_wire0),
- .q (sub_wire1)
- // synopsys translate_off
- ,
- .aclr (),
- .almost_empty (),
- .almost_full (),
- .full (),
- .usedw ()
- // synopsys translate_on
- );
- defparam
- scfifo_component.add_ram_output_register = "OFF",
- scfifo_component.intended_device_family = "Cyclone",
- scfifo_component.lpm_numwords = 2048,
- scfifo_component.lpm_showahead = "OFF",
- scfifo_component.lpm_type = "scfifo",
- scfifo_component.lpm_width = 32,
- scfifo_component.lpm_widthu = 11,
- scfifo_component.overflow_checking = "OFF",
- scfifo_component.underflow_checking = "OFF",
- scfifo_component.use_eab = "ON";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "2048"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "32"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_bb.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_waveforms.html FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_wave*.jpg FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v
deleted file mode 100644
index 1023d2f25..000000000
--- a/gr-radar-mono/src/fpga/lib/radar.v
+++ /dev/null
@@ -1,81 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-`include "../lib/radar_config.vh"
-
-module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
- tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
- rx_adc_i_i,rx_adc_q_i,
- rx_strobe_o,rx_ech_i_o,rx_ech_q_o,io_tx_ena_o);
-
- // System interface
- input clk_i; // Master clock @ 64 MHz
- input [6:0] saddr_i; // Configuration bus address
- input [31:0] sdata_i; // Configuration bus data
- input s_strobe_i; // Configuration bus write
-
- // Transmit subsystem
- output tx_side_o; // Transmitter slot
- output tx_strobe_o; // Generate an transmitter output sample
- output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
- output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
- output io_tx_ena_o; // Transmit/Receive switching
-
- // Receive subsystem
- input [15:0] rx_adc_i_i; // I channel input from ADC
- input [15:0] rx_adc_q_i; // Q channel input from ADC
- output rx_strobe_o; // Indicates output samples ready for Rx FIFO
- output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO
- output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO
-
- // Application control
- wire reset; // Master application reset
- wire tx_side; // Transmitter slot
- wire debug_enabled; // Enable debugging mode;
- wire tx_enable; // Transmitter enable
- wire rx_enable; // Receiver enable
- wire tx_ctrl; // Transmitter on control
- wire rx_ctrl; // Receiver on control
- wire [15:0] pulse_num; // Count of pulses since tx_enabled
-
- // Configuration
- wire [15:0] ampl; // Pulse amplitude
- wire [31:0] fstart; // Chirp start frequency
- wire [31:0] fincr; // Chirp per strobe frequency increment
-
- radar_control controller
- (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
- .reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled),
- .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
- .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num),
- .io_tx_ena_o(io_tx_ena_o));
-
- radar_tx transmitter
- ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o),
- .ampl_i(ampl),.fstart_i(fstart),.fincr_i(fincr),
- .tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
-
- radar_rx receiver
- ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled),
- .pulse_num_i(pulse_num),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
- .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
-
-endmodule // radar
diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh
deleted file mode 100644
index 89a336735..000000000
--- a/gr-radar-mono/src/fpga/lib/radar_config.vh
+++ /dev/null
@@ -1,41 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-`include "../../../../usrp/firmware/include/fpga_regs_common.v"
-`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-
-`define FR_RADAR_MODE `FR_USER_0
-`define bmFR_RADAR_MODE_RESET 32'b1 << 0
-`define bmFR_RADAR_TXSIDE 32'b1 << 1
-`define bmFR_RADAR_LOOP 32'b1 << 2
-`define bmFR_RADAR_META 32'b1 << 3
-`define bmFR_RADAR_DERAMP 32'b1 << 4
-`define bmFR_RADAR_CHIRPS 32'b11 << 5
-`define bmFR_RADAR_DEBUG 32'b1 << 7
-
-`define FR_RADAR_TON `FR_USER_1
-`define FR_RADAR_TSW `FR_USER_2
-`define FR_RADAR_TLOOK `FR_USER_3
-`define FR_RADAR_TIDLE `FR_USER_4
-`define FR_RADAR_AMPL `FR_USER_5
-`define FR_RADAR_FSTART `FR_USER_6
-`define FR_RADAR_FINCR `FR_USER_7
-`define FR_RADAR_ATRDEL `FR_USER_8
diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v
deleted file mode 100644
index 05b78198d..000000000
--- a/gr-radar-mono/src/fpga/lib/radar_control.v
+++ /dev/null
@@ -1,166 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-`include "../lib/radar_config.vh"
-
-module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
- tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
- ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
-
- // System interface
- input clk_i; // Master clock @ 64 MHz
- input [6:0] saddr_i; // Configuration bus address
- input [31:0] sdata_i; // Configuration bus data
- input s_strobe_i; // Configuration bus write
-
- // Control and configuration outputs
- output reset_o;
- output tx_side_o;
- output dbg_o;
- output tx_strobe_o;
- output tx_ctrl_o;
- output rx_ctrl_o;
- output [15:0] ampl_o;
- output [31:0] fstart_o;
- output [31:0] fincr_o;
- output [15:0] pulse_num_o;
- output io_tx_ena_o;
-
- // Internal configuration
- wire lp_ena;
- wire md_ena;
- wire dr_ena;
- wire [1:0] chirps;
- wire [15:0] t_on;
- wire [15:0] t_sw;
- wire [15:0] t_look;
- wire [31:0] t_idle;
- wire [31:0] atrdel;
-
- // Configuration from host
- wire [31:0] mode;
- setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(mode));
- assign reset_o = mode[0];
- assign tx_side_o = mode[1];
- assign lp_ena = mode[2];
- assign md_ena = mode[3];
- assign dr_ena = mode[4];
- assign chirps = mode[6:5];
- assign dbg_o = mode[7];
-
- setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(t_on));
-
- setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(t_sw));
-
- setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(t_look));
-
- setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(t_idle));
-
- setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(ampl_o));
-
- setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(fstart_o));
-
- setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(fincr_o));
-
- setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
- .out(atrdel));
-
- // Pulse state machine
- `define ST_ON 4'b0001
- `define ST_SW 4'b0010
- `define ST_LOOK 4'b0100
- `define ST_IDLE 4'b1000
-
- reg [3:0] state;
- reg [31:0] count;
- reg [15:0] pulse_num_o;
-
- always @(posedge clk_i)
- if (reset_o)
- begin
- state <= `ST_ON;
- count <= 32'b0;
- pulse_num_o <= 16'b0;
- end
- else
- case (state)
- `ST_ON:
- if (count == {16'b0,t_on})
- begin
- state <= `ST_SW;
- count <= 32'b0;
- pulse_num_o <= pulse_num_o + 16'b1;
- end
- else
- count <= count + 32'b1;
-
- `ST_SW:
- if (count == {16'b0,t_sw})
- begin
- state <= `ST_LOOK;
- count <= 32'b0;
- end
- else
- count <= count + 32'b1;
-
- `ST_LOOK:
- if (count == {16'b0,t_look})
- begin
- state <= `ST_IDLE;
- count <= 32'b0;
- end
- else
- count <= count + 32'b1;
-
- `ST_IDLE:
- if (count == t_idle)
- begin
- state <= `ST_ON;
- count <= 32'b0;
- end
- else
- count <= count + 32'b1;
-
- default: // Invalid state, reset state machine
- begin
- state <= `ST_ON;
- count <= 32'b0;
- end
- endcase
-
- assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
- assign tx_ctrl_o = (state == `ST_ON);
- assign rx_ctrl_o = (state == `ST_LOOK);
-
- // Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
- atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
- .tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
- .atr_tx_o(io_tx_ena_o));
-
-endmodule // radar_control
diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v
deleted file mode 100644
index 4b0b83c49..000000000
--- a/gr-radar-mono/src/fpga/lib/radar_rx.v
+++ /dev/null
@@ -1,109 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-`include "../../../../usrp/firmware/include/fpga_regs_common.v"
-`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-
-module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i,
- rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
-
- input clk_i;
- input rst_i;
- input ena_i;
- input dbg_i;
-
- input [15:0] rx_in_i_i;
- input [15:0] rx_in_q_i;
- input [15:0] pulse_num_i;
-
- output [15:0] rx_i_o;
- output [15:0] rx_q_o;
- output reg rx_strobe_o;
-
- reg [15:0] count;
-
- always @(posedge clk_i)
- if (rst_i | ~ena_i)
- count <= 16'b0;
- else
- count <= count + 16'b1;
-
- wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i};
-
- // Buffer incoming samples every clock
- wire [31:0] fifo_out;
- reg fifo_ack;
- wire fifo_empty;
-
-// Use model if simulating, otherwise Altera Megacell
-`ifdef SIMULATION
- fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i),
- .data(fifo_inp),.wrreq(ena_i),
- .rdreq(fifo_ack),.q(fifo_out),
- .empty(fifo_empty));
-`else
- fifo32_2k buffer(.clock(clk_i),.sclr(rst_i),
- .data(fifo_inp),.wrreq(ena_i),
- .rdreq(fifo_ack),.q(fifo_out),
- .empty(fifo_empty));
-`endif
-
- // Write samples to rx_fifo every third clock
- `define ST_FIFO_IDLE 3'b001
- `define ST_FIFO_STROBE 3'b010
- `define ST_FIFO_ACK 3'b100
-
- reg [2:0] state;
-
- always @(posedge clk_i)
- if (rst_i)
- begin
- state <= `ST_FIFO_IDLE;
- rx_strobe_o <= 1'b0;
- fifo_ack <= 1'b0;
- end
- else
- case (state)
- `ST_FIFO_IDLE:
- if (!fifo_empty)
- begin
- // Tell rx_fifo sample is ready
- rx_strobe_o <= 1'b1;
- state <= `ST_FIFO_STROBE;
- end
- `ST_FIFO_STROBE:
- begin
- rx_strobe_o <= 1'b0;
- // Ack our FIFO
- fifo_ack <= 1'b1;
- state <= `ST_FIFO_ACK;
- end
- `ST_FIFO_ACK:
- begin
- fifo_ack <= 1'b0;
- state <= `ST_FIFO_IDLE;
- end
- endcase // case(state)
-
- assign rx_i_o = fifo_out[31:16];
- assign rx_q_o = fifo_out[15:0];
-
-endmodule // radar_rx
diff --git a/gr-radar-mono/src/fpga/lib/radar_tx.v b/gr-radar-mono/src/fpga/lib/radar_tx.v
deleted file mode 100644
index c20dd0c1a..000000000
--- a/gr-radar-mono/src/fpga/lib/radar_tx.v
+++ /dev/null
@@ -1,59 +0,0 @@
-// -*- verilog -*-
-//
-// USRP - Universal Software Radio Peripheral
-//
-// Copyright (C) 2007 Corgan Enterprises LLC
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program; if not, write to the Free Software
-// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
-//
-
-module radar_tx(clk_i,rst_i,ena_i,strobe_i,
- ampl_i,fstart_i,fincr_i,
- tx_i_o,tx_q_o);
-
- // System control
- input clk_i;
- input rst_i;
- input ena_i;
- input strobe_i;
-
- // Configuration
- input [15:0] ampl_i;
- input [31:0] fstart_i;
- input [31:0] fincr_i;
-
- // Chirp output
- output [13:0] tx_i_o;
- output [13:0] tx_q_o;
- wire [15:0] cordic_i, cordic_q;
-
- // Chirp generator
- reg [31:0] freq;
-
- always @(posedge clk_i)
- if (rst_i | ~ena_i)
- freq <= fstart_i;
- else
- if (strobe_i)
- freq <= freq + fincr_i;
-
- cordic_nco nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
- .ampl_i(ampl_i),.freq_i(freq),.phs_i(0),
- .data_i_o(cordic_i),.data_q_o(cordic_q));
-
- assign tx_i_o = cordic_i[13:0];
- assign tx_q_o = cordic_q[13:0];
-
-endmodule // radar_tx
generated by cgit (git 2.34.1) at 2024-12-22 01:00:16 +0000