diff options
Diffstat (limited to 'gr-radar-mono/src/fpga/lib')
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/cordic_nco.v | 2 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar.v | 32 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar_config.vh | 10 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar_control.v | 117 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar_rx.v | 6 | ||||
| -rw-r--r-- | gr-radar-mono/src/fpga/lib/radar_tx.v | 27 |
6 files changed, 149 insertions, 45 deletions
diff --git a/gr-radar-mono/src/fpga/lib/cordic_nco.v b/gr-radar-mono/src/fpga/lib/cordic_nco.v index ef13aa2d8..b9858baf8 100644 --- a/gr-radar-mono/src/fpga/lib/cordic_nco.v +++ b/gr-radar-mono/src/fpga/lib/cordic_nco.v @@ -47,7 +47,7 @@ module cordic_nco(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,phs_i,data_i_o,data_q assign ampl = ena_i ? ampl_i : 16'b0; cordic tx_cordic - (.clock(clk_i),.reset(rst_in),.enable(strobe_i), + (.clock(clk_i),.reset(rst_i),.enable(strobe_i), .xi(ampl),.yi(16'b0),.zi(phase[31:16]), .xo(data_i_o),.yo(data_q_o),.zo()); diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v index c6690f4c7..2a0c08bb5 100644 --- a/gr-radar-mono/src/fpga/lib/radar.v +++ b/gr-radar-mono/src/fpga/lib/radar.v @@ -22,7 +22,7 @@ `include "../lib/radar_config.vh" module radar(clk_i,saddr_i,sdata_i,s_strobe_i, - tx_strobe_i,tx_dac_i_o,tx_dac_q_o, + tx_strobe_o,tx_dac_i_o,tx_dac_q_o, rx_strobe_i,rx_adc_i_i,rx_adc_q_i, rx_strobe_o,rx_ech_i_o,rx_ech_q_o); @@ -33,7 +33,7 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i, input s_strobe_i; // Configuration bus write // Transmit subsystem - input tx_strobe_i; // Generate an transmitter output sample + output tx_strobe_o; // Generate an transmitter output sample output [13:0] tx_dac_i_o; // I channel transmitter output to DAC output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC @@ -45,26 +45,30 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i, output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO + // Application control wire reset; // Master application reset wire tx_enable; // Transmitter enable wire rx_enable; // Receiver enable - - wire [15:0] ampl; - wire [31:0] freq; // temporary - + wire tx_ctrl; // Transmitter on control + wire rx_ctrl; // Receiver on control + + // Configuration + wire [15:0] ampl; // Pulse amplitude + wire [31:0] fstart; // Chirp start frequency + wire [31:0] fincr; // Chirp per strobe frequency increment + radar_control controller - (.clk_i(clk_i),.rst_i(1'b0),.ena_i(1'b1), - .s_strobe_i(s_strobe_i),.saddr_i(saddr_i),.sdata_i(sdata_i), - .reset_o(reset),.tx_ena_o(tx_enable),.rx_ena_o(rx_enable), - .ampl_o(ampl),.freq_o(freq)); + (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i), + .reset_o(reset),.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl), + .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr)); radar_tx transmitter - ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_enable), - .ampl_i(ampl),.freq_i(freq), - .strobe_i(tx_strobe_i),.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) ); + ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o), + .ampl_i(ampl),.fstart_i(fstart),.fincr_i(fincr), + .tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) ); radar_rx receiver - ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_enable), + ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl & 1'b0), // Disable receiver for now .strobe_i(rx_strobe_i),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i), .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) ); diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh index d17cda123..a06a51119 100644 --- a/gr-radar-mono/src/fpga/lib/radar_config.vh +++ b/gr-radar-mono/src/fpga/lib/radar_config.vh @@ -24,8 +24,12 @@ `define FR_RADAR_MODE `FR_USER_0 `define bmFR_RADAR_MODE_RESET 32'h0001 -`define bmFR_RADAR_MODE_TX 32'h0002 -`define bmFR_RADAR_MODE_RX 32'h0004 +`define FR_RADAR_TON `FR_USER_1 +`define FR_RADAR_TSW `FR_USER_2 +`define FR_RADAR_TLOOK `FR_USER_3 +`define FR_RADAR_TIDLE `FR_USER_4 `define FR_RADAR_AMPL `FR_USER_5 -`define FR_RADAR_FREQ1N `FR_USER_8 +`define FR_RADAR_FSTART `FR_USER_6 +`define FR_RADAR_FINCR `FR_USER_7 + diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v index 9aa2e217b..4f88645bb 100644 --- a/gr-radar-mono/src/fpga/lib/radar_control.v +++ b/gr-radar-mono/src/fpga/lib/radar_control.v @@ -21,39 +21,122 @@ `include "../lib/radar_config.vh" -module radar_control(clk_i,rst_i,ena_i,saddr_i,sdata_i,s_strobe_i, - reset_o,tx_ena_o,rx_ena_o,ampl_o,freq_o); +module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i, + reset_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o, + ampl_o,fstart_o,fincr_o); // System interface input clk_i; // Master clock @ 64 MHz - input rst_i; // Master reset - input ena_i; // Module level enable input [6:0] saddr_i; // Configuration bus address input [31:0] sdata_i; // Configuration bus data input s_strobe_i; // Configuration bus write - // Configuration outputs + // Control and configuration outputs output reset_o; - output tx_ena_o; - output rx_ena_o; - + output tx_strobe_o; + output tx_ctrl_o; + output rx_ctrl_o; output [15:0] ampl_o; - output [31:0] freq_o; - + output [31:0] fstart_o; + output [31:0] fincr_o; + // Internal configuration wire lp_ena; wire dr_ena; wire md_ena; - wire [1:0] chirps; + wire [1:0] chirps; + wire [15:0] t_on; + wire [15:0] t_sw; + wire [15:0] t_look; + wire [31:0] t_idle; // Configuration from host - setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out({chirps,md_ena,dr_ena,lp_ena,rx_ena_o,tx_ena_o,reset_o})); + setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out({chirps,md_ena,dr_ena,lp_ena,reset_o})); + + setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out(t_on)); + + setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out(t_sw)); + + setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out(t_look)); - setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(ampl_o)); + setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out(t_idle)); + + setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out(ampl_o)); + + setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out(fstart_o)); - setting_reg #(`FR_RADAR_FREQ1N) sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), - .out(freq_o)); + setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out(fincr_o)); + + // Pulse state machine + `define ST_ON 4'b0001 + `define ST_SW 4'b0010 + `define ST_LOOK 4'b0100 + `define ST_IDLE 4'b1000 + + reg [3:0] state; + reg [31:0] count; + + always @(posedge clk_i) + if (reset_o) + begin + state <= `ST_ON; + count <= 32'b0; + end + else + case (state) + `ST_ON: + if (count == {16'b0,t_on}) + begin + state <= `ST_SW; + count <= 32'b0; + end + else + count <= count + 32'b1; + + `ST_SW: + if (count == {16'b0,t_sw}) + begin + state <= `ST_LOOK; + count <= 32'b0; + end + else + count <= count + 24'b1; + + `ST_LOOK: + if (count == {16'b0,t_look}) + begin + state <= `ST_IDLE; + count <= 32'b0; + end + else + count <= count + 32'b1; + + `ST_IDLE: + if (count == t_idle) + begin + state <= `ST_ON; + count <= 24'b0; + end + else + count <= count + 32'b1; + + default: // Invalid state, reset state machine + begin + state <= `ST_ON; + count <= 32'b0; + end + endcase + + assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz + assign tx_ctrl_o = (state == `ST_ON); + assign rx_ctrl_o = (state == `ST_LOOK); endmodule // radar_control diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v index a6c7409f8..b559df699 100644 --- a/gr-radar-mono/src/fpga/lib/radar_rx.v +++ b/gr-radar-mono/src/fpga/lib/radar_rx.v @@ -22,8 +22,8 @@ `include "../../../../usrp/firmware/include/fpga_regs_common.v" `include "../../../../usrp/firmware/include/fpga_regs_standard.v" -module radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,rx_in_i_i,rx_in_q_i, - rx_i_o,rx_q_o,rx_strobe_o); +module radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i, + rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o); input clk_i; input rst_i; @@ -36,7 +36,7 @@ module radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,rx_in_i_i, input [15:0] rx_in_i_i; input [15:0] rx_in_q_i; - + output [15:0] rx_i_o; output [15:0] rx_q_o; output rx_strobe_o; diff --git a/gr-radar-mono/src/fpga/lib/radar_tx.v b/gr-radar-mono/src/fpga/lib/radar_tx.v index ffb16fa70..c20dd0c1a 100644 --- a/gr-radar-mono/src/fpga/lib/radar_tx.v +++ b/gr-radar-mono/src/fpga/lib/radar_tx.v @@ -19,7 +19,10 @@ // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // -module radar_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,tx_i_o,tx_q_o); +module radar_tx(clk_i,rst_i,ena_i,strobe_i, + ampl_i,fstart_i,fincr_i, + tx_i_o,tx_q_o); + // System control input clk_i; input rst_i; @@ -28,19 +31,29 @@ module radar_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,tx_i_o,tx_q_o); // Configuration input [15:0] ampl_i; - input [31:0] freq_i; + input [31:0] fstart_i; + input [31:0] fincr_i; - // Output + // Chirp output output [13:0] tx_i_o; output [13:0] tx_q_o; + wire [15:0] cordic_i, cordic_q; - wire [15:0] cordic_i, cordic_q; + // Chirp generator + reg [31:0] freq; + always @(posedge clk_i) + if (rst_i | ~ena_i) + freq <= fstart_i; + else + if (strobe_i) + freq <= freq + fincr_i; + cordic_nco nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i), - .ampl_i(ampl_i),.freq_i(freq_i),.phs_i(0), + .ampl_i(ampl_i),.freq_i(freq),.phs_i(0), .data_i_o(cordic_i),.data_q_o(cordic_q)); - assign tx_i_o = cordic_i[13:0]; - assign tx_q_o = cordic_q[13:0]; + assign tx_i_o = cordic_i[13:0]; + assign tx_q_o = cordic_q[13:0]; endmodule // radar_tx |