diff options
Diffstat (limited to 'gr-gpio/src/fpga/lib')
| -rw-r--r-- | gr-gpio/src/fpga/lib/.gitignore | 2 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/Makefile.am | 33 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/gpio_input.v | 80 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/integ_shifter.v | 68 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/integrator.v | 75 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/io_pins.v | 55 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/rx_chain.v | 121 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/rx_chain_dig.v | 43 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/tx_chain_dig.v | 42 |
9 files changed, 0 insertions, 519 deletions
diff --git a/gr-gpio/src/fpga/lib/.gitignore b/gr-gpio/src/fpga/lib/.gitignore deleted file mode 100644 index b336cc7ce..000000000 --- a/gr-gpio/src/fpga/lib/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/Makefile -/Makefile.in diff --git a/gr-gpio/src/fpga/lib/Makefile.am b/gr-gpio/src/fpga/lib/Makefile.am deleted file mode 100644 index 85fec113f..000000000 --- a/gr-gpio/src/fpga/lib/Makefile.am +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright 2007 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -include $(top_srcdir)/Makefile.common - -SUBDIRS = - -EXTRA_DIST += \ - gpio_input.v \ - io_pins.v \ - rx_chain_dig.v \ - tx_chain_dig.v \ - integrator.v \ - integ_shifter.v \ - rx_chain.v
\ No newline at end of file diff --git a/gr-gpio/src/fpga/lib/gpio_input.v b/gr-gpio/src/fpga/lib/gpio_input.v deleted file mode 100644 index 871fe3263..000000000 --- a/gr-gpio/src/fpga/lib/gpio_input.v +++ /dev/null @@ -1,80 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module gpio_input - (input clock, input reset, input enable, - input out_strobe, - input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe, - input wire [15:0] io_rx_a_in, input wire [15:0] io_rx_b_in, - //input wire [15:0] io_tx_a_in, input wire [15:0] io_tx_b_in, - output reg rx_dig0_i, output reg rx_dig0_q, - output reg rx_dig1_i, output reg rx_dig1_q ); - - // Buffer at input to chip - - reg rx_dig_rx_a_a,rx_dig_rx_b_a,rx_dig_rx_a_b,rx_dig_rx_b_b; - //TODO possibly use a flancter here - //This code can optionally be extended to do streaming input from gpio of tx boards - //The code can also be extended to input more bits - - always @(posedge clock) - begin - //This is the first point where is determined which physical input gpio pins are used for streaming digital input - //The other point is the code which overrides these pins as input (oe = 0) - //rx_dig_tx_a_a <= #1 io_tx_a_in[14]; - //rx_dig_tx_b_a <= #1 io_tx_a_in[15]; - rx_dig_rx_a_a <= #1 io_rx_a_in[14]; - rx_dig_rx_b_a <= #1 io_rx_a_in[15]; - //rx_dig_tx_a_b <= #1 io_tx_b_in[14]; - //rx_dig_tx_b_b <= #1 io_tx_b_in[15]; - rx_dig_rx_a_b <= #1 io_rx_b_in[14]; - rx_dig_rx_b_b <= #1 io_rx_b_in[15]; - end - - // Now mux to the appropriate outputs - wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux; - wire rx_realsignals; - wire [3:0] rx_numchan;//not used here - //TODO This setting reg readout is a duplicate of the one in adc_interface.v. - // Change code so this is done in only one place, or give this code its own register. - setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr), - .in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]})); - //assign rx_numchan[0] = 1'b0; - - always @(posedge clock) - if (out_strobe) //out_strobe determines the time at which the digital inputs are sampled (with a delay of one sample) - begin - rx_dig0_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - rx_dig0_q <= #1 rx_realsignals ? 1'b0 : ddc0mux[3] ? (ddc0mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - rx_dig1_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - rx_dig1_q <= #1 rx_realsignals ? 1'b0 : ddc1mux[3] ? (ddc1mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig2_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig2_q <= #1 rx_realsignals ? 1'b0 : ddc2mux[3] ? (ddc2mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig3_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - //rx_dig3_q <= #1 rx_realsignals ? 1'b0 : ddc3mux[3] ? (ddc3mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); - end - -endmodule // gpio_input - - diff --git a/gr-gpio/src/fpga/lib/integ_shifter.v b/gr-gpio/src/fpga/lib/integ_shifter.v deleted file mode 100644 index 1ad0504cb..000000000 --- a/gr-gpio/src/fpga/lib/integ_shifter.v +++ /dev/null @@ -1,68 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - - -// NOTE: This only works for a max decim rate of 256 -// NOTE: Signal "rate" is ONE LESS THAN the actual rate - -module integ_shifter(rate,signal_in,signal_out); - parameter bw = 16; - parameter maxbitgain = 8; - - input [7:0] rate; - input wire [bw+maxbitgain-1:0] signal_in; - output reg [bw-1:0] signal_out; - - reg [3:0] bitgain; - - // Nearest without overflow -- ceil(log2(rate+1)) - always @* - if (rate >= 8'd128) - bitgain = 8; - else if (rate >= 8'd64) - bitgain = 7; - else if (rate >= 8'd32) - bitgain = 6; - else if (rate >= 8'd16) - bitgain = 5; - else if (rate >= 8'd8) - bitgain = 4; - else if (rate >= 8'd4) - bitgain = 3; - else if (rate >= 8'd2) - bitgain = 2; - else - bitgain = 1; - - always @* - case(bitgain) - 5'd1 : signal_out = signal_in[1+bw-1:1]; - 5'd2 : signal_out = signal_in[2+bw-1:2]; - 5'd3 : signal_out = signal_in[3+bw-1:3]; - 5'd4 : signal_out = signal_in[4+bw-1:4]; - 5'd5 : signal_out = signal_in[5+bw-1:5]; - 5'd6 : signal_out = signal_in[6+bw-1:6]; - 5'd7 : signal_out = signal_in[7+bw-1:7]; - default : signal_out = signal_in[8+bw-1:8]; - endcase // case(shift) - -endmodule // integ_shifter diff --git a/gr-gpio/src/fpga/lib/integrator.v b/gr-gpio/src/fpga/lib/integrator.v deleted file mode 100644 index 22357a565..000000000 --- a/gr-gpio/src/fpga/lib/integrator.v +++ /dev/null @@ -1,75 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Integrate and dump decimation filter -// -// Functionally equivalent to single-stage CIC decimator, simpler code -// Results in single sample impulse response at decimated rate - -module integrator - ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out); - parameter bw = 16; - parameter maxbitgain = 8; - - input clock; - input reset; - input enable; - input [7:0] rate; - input strobe_in; - input strobe_out; - - input [bw-1:0] signal_in; - wire [bw-1:0] signal_out_unreg; - output [bw-1:0] signal_out; - reg [bw-1:0] signal_out; - - wire [bw+maxbitgain-1:0] signal_in_ext; - reg [bw+maxbitgain-1:0] accum; - reg [bw+maxbitgain-1:0] dump; - - sign_extend #(bw,bw+maxbitgain) - ext_input (.in(signal_in),.out(signal_in_ext)); - - // Integrate samples, dump on strobe out - always @(posedge clock) - if (reset | ~enable) - begin - accum <= 0; - dump <= 0; - end - else if (enable && strobe_in) - if (~strobe_out) - accum <= accum + signal_in_ext; - else - begin - dump <= accum; - accum <= signal_in_ext; - end - - // Normalize for integration bit gain - integ_shifter #(bw) - shifter(rate,dump,signal_out_unreg); - - always @(posedge clock) - signal_out <= #1 signal_out_unreg; - -endmodule // integrator diff --git a/gr-gpio/src/fpga/lib/io_pins.v b/gr-gpio/src/fpga/lib/io_pins.v deleted file mode 100644 index 9d857902f..000000000 --- a/gr-gpio/src/fpga/lib/io_pins.v +++ /dev/null @@ -1,55 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2005,2006 Matt Ettus -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -`include "../../../../usrp/firmware/include/fpga_regs_common.v" -`include "../../../../usrp/firmware/include/fpga_regs_standard.v" - -module io_pins - ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3, - input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3, - input wire [15:0] io_0_force_output, input wire [15:0] io_2_force_output, - input wire [15:0] io_1_force_input, input wire [15:0] io_3_force_input, - input clock, input rx_reset, input tx_reset, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe); - - reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe; - - bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe | io_0_force_output),.reg_val(reg_0)); - bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe & (~io_1_force_input)),.reg_val(reg_1)); - bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe | io_2_force_output),.reg_val(reg_2)); - bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe & (~io_3_force_input)),.reg_val(reg_3)); - - // Upper 16 bits are mask for lower 16 - always @(posedge clock) - if(serial_strobe) - case(serial_addr) - `FR_OE_0 : io_0_oe - <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_1 : io_1_oe - <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_2 : io_2_oe - <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - `FR_OE_3 : io_3_oe - <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); - endcase // case(serial_addr) - -endmodule // io_pins diff --git a/gr-gpio/src/fpga/lib/rx_chain.v b/gr-gpio/src/fpga/lib/rx_chain.v deleted file mode 100644 index 172e978de..000000000 --- a/gr-gpio/src/fpga/lib/rx_chain.v +++ /dev/null @@ -1,121 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2003 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Following defines conditionally include RX path circuitry - -`include "config.vh" // resolved relative to project root - -module rx_chain - (input clock, - input reset, - input enable, - input wire [7:0] decim_rate, - input sample_strobe, - input decimator_strobe, - output wire hb_strobe, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, - input wire [15:0] i_in, - input wire [15:0] q_in, - output wire [15:0] i_out, - output wire [15:0] q_out, - output wire [15:0] debugdata,output wire [15:0] debugctrl - ); - - parameter FREQADDR = 0; - parameter PHASEADDR = 0; - - wire [31:0] phase; - wire [15:0] bb_i, bb_q; - wire [15:0] hb_in_i, hb_in_q; - - assign debugdata = hb_in_i; - -`ifdef RX_NCO_ON - phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc - (.clk(clock),.reset(reset),.enable(enable), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .strobe(sample_strobe),.phase(phase) ); - - cordic rx_cordic - ( .clock(clock),.reset(reset),.enable(enable), - .xi(i_in),.yi(q_in),.zi(phase[31:16]), - .xo(bb_i),.yo(bb_q),.zo() ); -`else - assign bb_i = i_in; - assign bb_q = q_in; - assign sample_strobe = 1; -`endif // !`ifdef RX_NCO_ON - -`ifdef RX_INTEG_ON - integrator integ_decim_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_i),.signal_out(i_out) ); - - assign hb_strobe = decimator_strobe; -`else -`ifdef RX_CIC_ON - cic_decim cic_decim_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_i),.signal_out(hb_in_i) ); -`else - assign hb_in_i = bb_i; - assign decimator_strobe = sample_strobe; -`endif - -`ifdef RX_HB_ON - halfband_decim hbd_i_0 - ( .clock(clock),.reset(reset),.enable(enable), - .strobe_in(decimator_strobe),.strobe_out(hb_strobe), - .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) ); -`else - assign i_out = hb_in_i; - assign hb_strobe = decimator_strobe; -`endif -`endif // RX_INTEG_ON - -`ifdef RX_INTEG_ON - integrator integ_decim_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_q),.signal_out(q_out) ); -`else -`ifdef RX_CIC_ON - cic_decim cic_decim_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe), - .signal_in(bb_q),.signal_out(hb_in_q) ); -`else - assign hb_in_q = bb_q; -`endif - -`ifdef RX_HB_ON - halfband_decim hbd_q_0 - ( .clock(clock),.reset(reset),.enable(enable), - .strobe_in(decimator_strobe),.strobe_out(), - .data_in(hb_in_q),.data_out(q_out) ); -`else - assign q_out = hb_in_q; -`endif -`endif // RX_INTEG_ON - -endmodule // rx_chain diff --git a/gr-gpio/src/fpga/lib/rx_chain_dig.v b/gr-gpio/src/fpga/lib/rx_chain_dig.v deleted file mode 100644 index 4f760dded..000000000 --- a/gr-gpio/src/fpga/lib/rx_chain_dig.v +++ /dev/null @@ -1,43 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Following defines conditionally include RX path circuitry - -`include "../top/config.vh" // resolved relative to project root - -module rx_chain_dig - (input clock, - input reset, - input enable, - input wire [15:0] i_in_ana, - input wire [15:0] q_in_ana, - input wire i_in_dig, - input wire q_in_dig, - output wire [15:0] i_out, - output wire [15:0] q_out - ); - - //assign upper 15 bits of output to analog input, - // discards lsb of analog input and replace with digital input bit (which comes from gpio) - assign i_out = (enable)?{i_in_ana[15:1],i_in_dig}:i_in_ana; - assign q_out = (enable)?{q_in_ana[15:1],q_in_dig}:q_in_ana; - -endmodule // rx_chain_dig diff --git a/gr-gpio/src/fpga/lib/tx_chain_dig.v b/gr-gpio/src/fpga/lib/tx_chain_dig.v deleted file mode 100644 index 7001947f7..000000000 --- a/gr-gpio/src/fpga/lib/tx_chain_dig.v +++ /dev/null @@ -1,42 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2008 Corgan Enterprises LLC -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module tx_chain_dig - (input clock, - input reset, - input enable, - input wire [15:0] i_in, - input wire [15:0] q_in, - output wire [15:0] i_out_ana, - output wire [15:0] q_out_ana, - output wire i_out_dig, - output wire q_out_dig - ); - - //assign upper 15 bits to analog processing, discard lowest bit - //output lower two bits of I and Q as digital signal (to be output on gpio pins) - assign i_out_ana = (enable)?{i_in[15:1],1'b0}:i_in; - assign q_out_ana = (enable)?{q_in[15:1],1'b0}:q_in; - //wire out_dig = (enable)?{i_in[0],q_in[0]}:2'b00; - assign i_out_dig = (enable)?i_in[0]:1'b0; - assign q_out_dig = (enable)?q_in[0]:1'b0; - -endmodule // tx_chain_dig |