diff options
Diffstat (limited to 'gr-gpio/src/fpga/lib')
| -rw-r--r-- | gr-gpio/src/fpga/lib/Makefile.am | 28 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/gpio_input.v | 80 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/io_pins.v | 55 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/rx_chain_dig.v | 43 | ||||
| -rw-r--r-- | gr-gpio/src/fpga/lib/tx_chain_dig.v | 42 |
5 files changed, 248 insertions, 0 deletions
diff --git a/gr-gpio/src/fpga/lib/Makefile.am b/gr-gpio/src/fpga/lib/Makefile.am new file mode 100644 index 000000000..db5fbd4ad --- /dev/null +++ b/gr-gpio/src/fpga/lib/Makefile.am @@ -0,0 +1,28 @@ +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +SUBDIRS = + +EXTRA_DIST = \ + gpio_input.v \ + io_pins.v \ + rx_chain_dig.v \ + tx_chain_dig.v
\ No newline at end of file diff --git a/gr-gpio/src/fpga/lib/gpio_input.v b/gr-gpio/src/fpga/lib/gpio_input.v new file mode 100644 index 000000000..871fe3263 --- /dev/null +++ b/gr-gpio/src/fpga/lib/gpio_input.v @@ -0,0 +1,80 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2008 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +`include "../../../../usrp/firmware/include/fpga_regs_common.v" +`include "../../../../usrp/firmware/include/fpga_regs_standard.v" + +module gpio_input + (input clock, input reset, input enable, + input out_strobe, + input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe, + input wire [15:0] io_rx_a_in, input wire [15:0] io_rx_b_in, + //input wire [15:0] io_tx_a_in, input wire [15:0] io_tx_b_in, + output reg rx_dig0_i, output reg rx_dig0_q, + output reg rx_dig1_i, output reg rx_dig1_q ); + + // Buffer at input to chip + + reg rx_dig_rx_a_a,rx_dig_rx_b_a,rx_dig_rx_a_b,rx_dig_rx_b_b; + //TODO possibly use a flancter here + //This code can optionally be extended to do streaming input from gpio of tx boards + //The code can also be extended to input more bits + + always @(posedge clock) + begin + //This is the first point where is determined which physical input gpio pins are used for streaming digital input + //The other point is the code which overrides these pins as input (oe = 0) + //rx_dig_tx_a_a <= #1 io_tx_a_in[14]; + //rx_dig_tx_b_a <= #1 io_tx_a_in[15]; + rx_dig_rx_a_a <= #1 io_rx_a_in[14]; + rx_dig_rx_b_a <= #1 io_rx_a_in[15]; + //rx_dig_tx_a_b <= #1 io_tx_b_in[14]; + //rx_dig_tx_b_b <= #1 io_tx_b_in[15]; + rx_dig_rx_a_b <= #1 io_rx_b_in[14]; + rx_dig_rx_b_b <= #1 io_rx_b_in[15]; + end + + // Now mux to the appropriate outputs + wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux; + wire rx_realsignals; + wire [3:0] rx_numchan;//not used here + //TODO This setting reg readout is a duplicate of the one in adc_interface.v. + // Change code so this is done in only one place, or give this code its own register. + setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr), + .in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]})); + //assign rx_numchan[0] = 1'b0; + + always @(posedge clock) + if (out_strobe) //out_strobe determines the time at which the digital inputs are sampled (with a delay of one sample) + begin + rx_dig0_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + rx_dig0_q <= #1 rx_realsignals ? 1'b0 : ddc0mux[3] ? (ddc0mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + rx_dig1_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + rx_dig1_q <= #1 rx_realsignals ? 1'b0 : ddc1mux[3] ? (ddc1mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + //rx_dig2_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + //rx_dig2_q <= #1 rx_realsignals ? 1'b0 : ddc2mux[3] ? (ddc2mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + //rx_dig3_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + //rx_dig3_q <= #1 rx_realsignals ? 1'b0 : ddc3mux[3] ? (ddc3mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a); + end + +endmodule // gpio_input + + diff --git a/gr-gpio/src/fpga/lib/io_pins.v b/gr-gpio/src/fpga/lib/io_pins.v new file mode 100644 index 000000000..9d857902f --- /dev/null +++ b/gr-gpio/src/fpga/lib/io_pins.v @@ -0,0 +1,55 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2005,2006 Matt Ettus +// Copyright (C) 2008 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +`include "../../../../usrp/firmware/include/fpga_regs_common.v" +`include "../../../../usrp/firmware/include/fpga_regs_standard.v" + +module io_pins + ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3, + input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3, + input wire [15:0] io_0_force_output, input wire [15:0] io_2_force_output, + input wire [15:0] io_1_force_input, input wire [15:0] io_3_force_input, + input clock, input rx_reset, input tx_reset, + input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe); + + reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe; + + bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe | io_0_force_output),.reg_val(reg_0)); + bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe & (~io_1_force_input)),.reg_val(reg_1)); + bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe | io_2_force_output),.reg_val(reg_2)); + bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe & (~io_3_force_input)),.reg_val(reg_3)); + + // Upper 16 bits are mask for lower 16 + always @(posedge clock) + if(serial_strobe) + case(serial_addr) + `FR_OE_0 : io_0_oe + <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_1 : io_1_oe + <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_2 : io_2_oe + <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + `FR_OE_3 : io_3_oe + <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] ); + endcase // case(serial_addr) + +endmodule // io_pins diff --git a/gr-gpio/src/fpga/lib/rx_chain_dig.v b/gr-gpio/src/fpga/lib/rx_chain_dig.v new file mode 100644 index 000000000..4f760dded --- /dev/null +++ b/gr-gpio/src/fpga/lib/rx_chain_dig.v @@ -0,0 +1,43 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2008 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Following defines conditionally include RX path circuitry + +`include "../top/config.vh" // resolved relative to project root + +module rx_chain_dig + (input clock, + input reset, + input enable, + input wire [15:0] i_in_ana, + input wire [15:0] q_in_ana, + input wire i_in_dig, + input wire q_in_dig, + output wire [15:0] i_out, + output wire [15:0] q_out + ); + + //assign upper 15 bits of output to analog input, + // discards lsb of analog input and replace with digital input bit (which comes from gpio) + assign i_out = (enable)?{i_in_ana[15:1],i_in_dig}:i_in_ana; + assign q_out = (enable)?{q_in_ana[15:1],q_in_dig}:q_in_ana; + +endmodule // rx_chain_dig diff --git a/gr-gpio/src/fpga/lib/tx_chain_dig.v b/gr-gpio/src/fpga/lib/tx_chain_dig.v new file mode 100644 index 000000000..7001947f7 --- /dev/null +++ b/gr-gpio/src/fpga/lib/tx_chain_dig.v @@ -0,0 +1,42 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2008 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module tx_chain_dig + (input clock, + input reset, + input enable, + input wire [15:0] i_in, + input wire [15:0] q_in, + output wire [15:0] i_out_ana, + output wire [15:0] q_out_ana, + output wire i_out_dig, + output wire q_out_dig + ); + + //assign upper 15 bits to analog processing, discard lowest bit + //output lower two bits of I and Q as digital signal (to be output on gpio pins) + assign i_out_ana = (enable)?{i_in[15:1],1'b0}:i_in; + assign q_out_ana = (enable)?{q_in[15:1],1'b0}:q_in; + //wire out_dig = (enable)?{i_in[0],q_in[0]}:2'b00; + assign i_out_dig = (enable)?i_in[0]:1'b0; + assign q_out_dig = (enable)?q_in[0]:1'b0; + +endmodule // tx_chain_dig |