diff options
| -rw-r--r-- | usrp/host/include/usrp/db_wbxng.h | 6 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng.cc | 2 | ||||
| -rw-r--r-- | usrp2/fpga/control_lib/newfifo/fifo_2clock.v | 10 |
3 files changed, 6 insertions, 12 deletions
diff --git a/usrp/host/include/usrp/db_wbxng.h b/usrp/host/include/usrp/db_wbxng.h index 2158face2..8611d4787 100644 --- a/usrp/host/include/usrp/db_wbxng.h +++ b/usrp/host/include/usrp/db_wbxng.h @@ -41,12 +41,6 @@ public: protected: bool _lock_detect(); - - //virtual bool _compute_regs(double freq, int &retR, int &retcontrol, int &retN, double &retfreq); - int _compute_control_reg(); - int _refclk_divisor(); - double _refclk_freq(); - bool _set_pga(float pga_gain); int power_on() { return d_power_on; } diff --git a/usrp/host/lib/db_wbxng.cc b/usrp/host/lib/db_wbxng.cc index c23fc47ed..38c3a2886 100644 --- a/usrp/host/lib/db_wbxng.cc +++ b/usrp/host/lib/db_wbxng.cc @@ -86,7 +86,7 @@ wbxng_base::set_freq(double freq) nanosleep(&t, NULL); fprintf(stderr,"Setting WBXNG frequency, requested %d, obtained %f, lock_detect %d\n", - int_freq, freq_result, _lock_detect()); + int_freq, freq_result, d_common->_get_locked()); // FIXME // Offsetting the LO helps get the Tx carrier leakage out of the way. diff --git a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v index 07ae090f2..34c85ccb4 100644 --- a/usrp2/fpga/control_lib/newfifo/fifo_2clock.v +++ b/usrp2/fpga/control_lib/newfifo/fifo_2clock.v @@ -19,28 +19,28 @@ module fifo_2clock if(WIDTH==36) if(SIZE==9) fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if(SIZE==11) fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if(SIZE==6) fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if((WIDTH==19)|(WIDTH==18)) if(SIZE==4) fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate |