diff options
| -rw-r--r-- | usrp/host/lib/db_wbxng_adf4350.cc | 10 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng_adf4350_regs.cc | 10 | ||||
| -rw-r--r-- | usrp/host/lib/db_wbxng_adf4350_regs.h | 2 |
3 files changed, 14 insertions, 8 deletions
diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc index af4eac573..2cec972b0 100644 --- a/usrp/host/lib/db_wbxng_adf4350.cc +++ b/usrp/host/lib/db_wbxng_adf4350.cc @@ -34,7 +34,7 @@ #define MAX_RF_DIV uint8_t(16) /* max rf divider, divides rf output */ #define MIN_VCO_FREQ FREQ_C(2.2e9) /* minimum vco freq */ #define MAX_VCO_FREQ FREQ_C(4.4e9) /* minimum vco freq */ -#define MAX_FREQ MAX_VCO_FREQ /* upper bound freq (rf div = 1) */ +#define MAX_FREQ DIV_ROUND(MAX_VCO_FREQ, 1) /* upper bound freq (rf div = 1) */ #define MIN_FREQ DIV_ROUND(MIN_VCO_FREQ, MAX_RF_DIV) /* calculated lower bound freq */ #define CE_PIN (1 << 3) @@ -133,6 +133,12 @@ adf4350::_set_freq(freq_t freq) { /* Set the frequency by setting int, frac, mod, r, div */ if (freq > MAX_FREQ || freq < MIN_FREQ) return false; + int min_int_div = 23; + d_regs->d_prescaler = 0; + if (freq > FREQ_C(3e9)) { + min_int_div = 75; + d_regs->d_prescaler = 1; + } /* Ramp up the RF divider until the VCO is within range. */ d_regs->d_divider_select = 0; while (freq < MIN_VCO_FREQ){ @@ -159,7 +165,7 @@ adf4350::_set_freq(freq_t freq) d_regs->d_mod, d_regs->d_10_bit_r_counter, (1 << d_regs->d_divider_select) ); */ - }while(d_regs->d_int < MIN_INT_DIV); + }while(d_regs->d_int < min_int_div); /* calculate the band select so PFD is under 125 KHz */ d_regs->d_8_bit_band_select_clock_divider_value = \ INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1; diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.cc b/usrp/host/lib/db_wbxng_adf4350_regs.cc index 11dcf8816..696b7c1d4 100644 --- a/usrp/host/lib/db_wbxng_adf4350_regs.cc +++ b/usrp/host/lib/db_wbxng_adf4350_regs.cc @@ -9,7 +9,6 @@ /* reg 0 */ /* reg 1 */ -const uint8_t adf4350_regs::s_prescaler = 0; const uint16_t adf4350_regs::s_phase = 0; /* reg 2 */ const uint8_t adf4350_regs::s_low_noise_and_low_spur_modes = 0; @@ -32,9 +31,9 @@ const uint16_t adf4350_regs::s_12_bit_clock_divider_value = 0; const uint8_t adf4350_regs::s_feedback_select = 1; const uint8_t adf4350_regs::s_vco_power_down = 0; const uint8_t adf4350_regs::s_mtld = 0; -const uint8_t adf4350_regs::s_aux_output_select = 0; -const uint8_t adf4350_regs::s_aux_output_enable = 1; -const uint8_t adf4350_regs::s_aux_output_power = 3; +const uint8_t adf4350_regs::s_aux_output_select = 1; +const uint8_t adf4350_regs::s_aux_output_enable = 0; +const uint8_t adf4350_regs::s_aux_output_power = 0; const uint8_t adf4350_regs::s_rf_output_enable = 1; const uint8_t adf4350_regs::s_output_power = 3; /* reg 5 */ @@ -47,6 +46,7 @@ adf4350_regs::adf4350_regs(adf4350* _adf4350){ d_int = uint16_t(100); d_frac = 0; /* reg 1 */ + d_prescaler = uint8_t(0); d_mod = uint16_t(0xfff); /* max fractional accuracy */ /* reg 2 */ d_10_bit_r_counter = uint16_t(2); @@ -73,7 +73,7 @@ adf4350_regs::_load_register(uint8_t addr){ _reg_shift(d_int, 15) | _reg_shift(d_frac, 3)); break; case 1: data = ( - _reg_shift(s_prescaler, 27) | + _reg_shift(d_prescaler, 27) | _reg_shift(s_phase, 15) | _reg_shift(d_mod, 3)); break; case 2: data = ( diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.h b/usrp/host/lib/db_wbxng_adf4350_regs.h index dc941ee87..3973b4d6b 100644 --- a/usrp/host/lib/db_wbxng_adf4350_regs.h +++ b/usrp/host/lib/db_wbxng_adf4350_regs.h @@ -25,7 +25,7 @@ public: uint16_t d_int; uint16_t d_frac; /* reg 1 */ - static const uint8_t s_prescaler; + uint8_t d_prescaler; static const uint16_t s_phase; uint16_t d_mod; /* reg 2 */ |