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-rw-r--r--usrp2/firmware/apps/burnrev30.c229
-rw-r--r--usrp2/firmware/apps/burnrev31.c229
-rw-r--r--usrp2/firmware/apps/burnrev40.c9
3 files changed, 33 insertions, 434 deletions
diff --git a/usrp2/firmware/apps/burnrev30.c b/usrp2/firmware/apps/burnrev30.c
index d07213910..e91c35c09 100644
--- a/usrp2/firmware/apps/burnrev30.c
+++ b/usrp2/firmware/apps/burnrev30.c
@@ -39,224 +39,11 @@
#include <usrp2_i2c_addr.h>
#include <clocks.h>
#include "sd.h"
+#include "mdelay.h"
#define HW_REV_MAJOR 3
#define HW_REV_MINOR 0
-#define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
-
-#if (FW_SETS_SEQNO)
-static int fw_seqno; // used when f/w is filling in sequence numbers
-#endif
-
-
-/*
- * Full duplex Tx and Rx between ethernet and DSP pipelines
- *
- * Buffer 1 is used by the cpu to send frames to the host.
- * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
- * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
- */
-//#define CPU_RX_BUF 0 // eth -> cpu
-
-#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
-#define DSP_RX_BUF_1 3 // dsp rx -> eth
-#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
-#define DSP_TX_BUF_1 5 // eth -> dsp tx
-
-/*
- * ================================================================
- * configure DSP TX double buffering state machine (eth -> dsp)
- * ================================================================
- */
-
-// 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
-// DSP Tx reads word0 (flags) + timestamp followed by samples
-
-#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
-
-// Receive from ethernet
-buf_cmd_args_t dsp_tx_recv_args = {
- PORT_ETH,
- 0,
- BP_LAST_LINE
-};
-
-// send to DSP Tx
-buf_cmd_args_t dsp_tx_send_args = {
- PORT_DSP,
- DSP_TX_FIRST_LINE, // starts just past transport header
- 0 // filled in from last_line register
-};
-
-dbsm_t dsp_tx_sm; // the state machine
-
-/*
- * ================================================================
- * configure DSP RX double buffering state machine (dsp -> eth)
- * ================================================================
- */
-
-// 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
-// DSP Rx writes timestamp followed by nlines_per_frame of samples
-#define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
-
-// receive from DSP
-buf_cmd_args_t dsp_rx_recv_args = {
- PORT_DSP,
- DSP_RX_FIRST_LINE,
- BP_LAST_LINE
-};
-
-// send to ETH
-buf_cmd_args_t dsp_rx_send_args = {
- PORT_ETH,
- 0, // starts with ethernet header in line 0
- 0, // filled in from list_line register
-};
-
-dbsm_t dsp_rx_sm; // the state machine
-
-
-// The mac address of the host we're sending to.
-u2_mac_addr_t host_mac_addr;
-
-
-// variables for streaming mode
-
-static bool streaming_p = false;
-static unsigned int streaming_items_per_frame = 0;
-static int streaming_frame_count = 0;
-#define FRAMES_PER_CMD 1000
-
-bool is_streaming(void){ return streaming_p; }
-
-// ----------------------------------------------------------------
-
-
-void
-restart_streaming(void)
-{
- // setup RX DSP regs
- dsp_rx_regs->clear_state = 1; // reset
-
- streaming_p = true;
- streaming_frame_count = FRAMES_PER_CMD;
-
- dsp_rx_regs->rx_command =
- MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
- streaming_items_per_frame,
- 1, 1); // set "chain" bit
-
- // kick off the state machine
- dbsm_start(&dsp_rx_sm);
-
- dsp_rx_regs->rx_time = 0; // enqueue first of two commands
-
- // make sure this one and the rest have the "now" and "chain" bits set.
- dsp_rx_regs->rx_command =
- MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
- streaming_items_per_frame,
- 1, 1);
-
- dsp_rx_regs->rx_time = 0; // enqueue second command
-}
-
-void
-start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
-{
- host_mac_addr = *host; // remember who we're sending to
-
- /*
- * Construct ethernet header and word0 and preload into two buffers
- */
- u2_eth_packet_t pkt;
- memset(&pkt, 0, sizeof(pkt));
- pkt.ehdr.dst = *host;
- pkt.ehdr.ethertype = U2_ETHERTYPE;
- u2p_set_word0(&pkt.fixed, 0, 0);
- // DSP RX will fill in timestamp
-
- memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
- memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
-
-
- if (FW_SETS_SEQNO)
- fw_seqno = 0;
-
- streaming_items_per_frame = p->items_per_frame;
- restart_streaming();
-}
-
-
-void
-stop_rx_cmd(void)
-{
- streaming_p = false;
- dsp_rx_regs->clear_state = 1; // flush cmd queue
- bp_clear_buf(DSP_RX_BUF_0);
- bp_clear_buf(DSP_RX_BUF_1);
-}
-
-
-static void
-setup_tx()
-{
- dsp_tx_regs->clear_state = 1;
- bp_clear_buf(DSP_TX_BUF_0);
- bp_clear_buf(DSP_TX_BUF_1);
-
- int tx_scale = 256;
- int interp = 32;
-
- // setup some defaults
-
- dsp_tx_regs->freq = 0;
- dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
- dsp_tx_regs->interp_rate = interp;
-}
-
-
-#if (FW_SETS_SEQNO)
-/*
- * Debugging ONLY. This will be handled by the tx_protocol_engine.
- *
- * This is called when the DSP Rx chain has filled in a packet.
- * We set and increment the seqno, then return false, indicating
- * that we didn't handle the packet. A bit of a kludge
- * but it should work.
- */
-bool
-fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
-{
- uint32_t *p = buffer_ram(buf_this);
- uint32_t seqno = fw_seqno++;
-
- // KLUDGE all kinds of nasty magic numbers and embedded knowledge
- uint32_t t = p[4];
- t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
- p[4] = t;
-
- // queue up another rx command when required
- if (streaming_p && --streaming_frame_count == 0){
- streaming_frame_count = FRAMES_PER_CMD;
- dsp_rx_regs->rx_time = 0;
- }
-
- return false; // we didn't handle the packet
-}
-#endif
-
-
-inline static void
-buffer_irq_handler(unsigned irq)
-{
- uint32_t status = buffer_pool_status->status;
-
- dbsm_process_status(&dsp_tx_sm, status);
- dbsm_process_status(&dsp_rx_sm, status);
-}
-
int test_ram()
{
int i,j,k;
@@ -329,7 +116,7 @@ main(void)
{
u2_init();
- putstr("\nFactory Test TXRX\n");
+ putstr("\nFactory Test, Board Rev 3.0\n");
bool ok = true;
unsigned char maj = HW_REV_MAJOR;
@@ -350,8 +137,8 @@ main(void)
puts("SD OK\n");
else {
puts("SD FAIL\n");
- hal_finish();
- return 0;
+ //hal_finish();
+ //return 0;
}
if(test_ram())
puts("RAM OK\n");
@@ -364,4 +151,12 @@ main(void)
print_mac_addr(ethernet_mac_addr()->addr);
newline();
+ clocks_mimo_config(MC_WE_LOCK_TO_SMA);
+
+ while (!clocks_lock_detect()) {
+ puts("No Lock");
+ mdelay(1000);
+ }
+ puts("Clock Locked\n");
+
}
diff --git a/usrp2/firmware/apps/burnrev31.c b/usrp2/firmware/apps/burnrev31.c
index 3f161353a..2a58bdfe5 100644
--- a/usrp2/firmware/apps/burnrev31.c
+++ b/usrp2/firmware/apps/burnrev31.c
@@ -39,224 +39,11 @@
#include <usrp2_i2c_addr.h>
#include <clocks.h>
#include "sd.h"
+#include "mdelay.h"
#define HW_REV_MAJOR 3
#define HW_REV_MINOR 1
-#define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
-
-#if (FW_SETS_SEQNO)
-static int fw_seqno; // used when f/w is filling in sequence numbers
-#endif
-
-
-/*
- * Full duplex Tx and Rx between ethernet and DSP pipelines
- *
- * Buffer 1 is used by the cpu to send frames to the host.
- * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
- * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow
- */
-//#define CPU_RX_BUF 0 // eth -> cpu
-
-#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer)
-#define DSP_RX_BUF_1 3 // dsp rx -> eth
-#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer)
-#define DSP_TX_BUF_1 5 // eth -> dsp tx
-
-/*
- * ================================================================
- * configure DSP TX double buffering state machine (eth -> dsp)
- * ================================================================
- */
-
-// 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp)
-// DSP Tx reads word0 (flags) + timestamp followed by samples
-
-#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4)
-
-// Receive from ethernet
-buf_cmd_args_t dsp_tx_recv_args = {
- PORT_ETH,
- 0,
- BP_LAST_LINE
-};
-
-// send to DSP Tx
-buf_cmd_args_t dsp_tx_send_args = {
- PORT_DSP,
- DSP_TX_FIRST_LINE, // starts just past transport header
- 0 // filled in from last_line register
-};
-
-dbsm_t dsp_tx_sm; // the state machine
-
-/*
- * ================================================================
- * configure DSP RX double buffering state machine (dsp -> eth)
- * ================================================================
- */
-
-// 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0)
-// DSP Rx writes timestamp followed by nlines_per_frame of samples
-#define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1)
-
-// receive from DSP
-buf_cmd_args_t dsp_rx_recv_args = {
- PORT_DSP,
- DSP_RX_FIRST_LINE,
- BP_LAST_LINE
-};
-
-// send to ETH
-buf_cmd_args_t dsp_rx_send_args = {
- PORT_ETH,
- 0, // starts with ethernet header in line 0
- 0, // filled in from list_line register
-};
-
-dbsm_t dsp_rx_sm; // the state machine
-
-
-// The mac address of the host we're sending to.
-u2_mac_addr_t host_mac_addr;
-
-
-// variables for streaming mode
-
-static bool streaming_p = false;
-static unsigned int streaming_items_per_frame = 0;
-static int streaming_frame_count = 0;
-#define FRAMES_PER_CMD 1000
-
-bool is_streaming(void){ return streaming_p; }
-
-// ----------------------------------------------------------------
-
-
-void
-restart_streaming(void)
-{
- // setup RX DSP regs
- dsp_rx_regs->clear_state = 1; // reset
-
- streaming_p = true;
- streaming_frame_count = FRAMES_PER_CMD;
-
- dsp_rx_regs->rx_command =
- MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
- streaming_items_per_frame,
- 1, 1); // set "chain" bit
-
- // kick off the state machine
- dbsm_start(&dsp_rx_sm);
-
- dsp_rx_regs->rx_time = 0; // enqueue first of two commands
-
- // make sure this one and the rest have the "now" and "chain" bits set.
- dsp_rx_regs->rx_command =
- MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame,
- streaming_items_per_frame,
- 1, 1);
-
- dsp_rx_regs->rx_time = 0; // enqueue second command
-}
-
-void
-start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p)
-{
- host_mac_addr = *host; // remember who we're sending to
-
- /*
- * Construct ethernet header and word0 and preload into two buffers
- */
- u2_eth_packet_t pkt;
- memset(&pkt, 0, sizeof(pkt));
- pkt.ehdr.dst = *host;
- pkt.ehdr.ethertype = U2_ETHERTYPE;
- u2p_set_word0(&pkt.fixed, 0, 0);
- // DSP RX will fill in timestamp
-
- memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
- memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
-
-
- if (FW_SETS_SEQNO)
- fw_seqno = 0;
-
- streaming_items_per_frame = p->items_per_frame;
- restart_streaming();
-}
-
-
-void
-stop_rx_cmd(void)
-{
- streaming_p = false;
- dsp_rx_regs->clear_state = 1; // flush cmd queue
- bp_clear_buf(DSP_RX_BUF_0);
- bp_clear_buf(DSP_RX_BUF_1);
-}
-
-
-static void
-setup_tx()
-{
- dsp_tx_regs->clear_state = 1;
- bp_clear_buf(DSP_TX_BUF_0);
- bp_clear_buf(DSP_TX_BUF_1);
-
- int tx_scale = 256;
- int interp = 32;
-
- // setup some defaults
-
- dsp_tx_regs->freq = 0;
- dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
- dsp_tx_regs->interp_rate = interp;
-}
-
-
-#if (FW_SETS_SEQNO)
-/*
- * Debugging ONLY. This will be handled by the tx_protocol_engine.
- *
- * This is called when the DSP Rx chain has filled in a packet.
- * We set and increment the seqno, then return false, indicating
- * that we didn't handle the packet. A bit of a kludge
- * but it should work.
- */
-bool
-fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false
-{
- uint32_t *p = buffer_ram(buf_this);
- uint32_t seqno = fw_seqno++;
-
- // KLUDGE all kinds of nasty magic numbers and embedded knowledge
- uint32_t t = p[4];
- t = (t & 0xffff00ff) | ((seqno & 0xff) << 8);
- p[4] = t;
-
- // queue up another rx command when required
- if (streaming_p && --streaming_frame_count == 0){
- streaming_frame_count = FRAMES_PER_CMD;
- dsp_rx_regs->rx_time = 0;
- }
-
- return false; // we didn't handle the packet
-}
-#endif
-
-
-inline static void
-buffer_irq_handler(unsigned irq)
-{
- uint32_t status = buffer_pool_status->status;
-
- dbsm_process_status(&dsp_tx_sm, status);
- dbsm_process_status(&dsp_rx_sm, status);
-}
-
int test_ram()
{
int i,j,k;
@@ -329,7 +116,7 @@ main(void)
{
u2_init();
- putstr("\nFactory Test TXRX\n");
+ putstr("\nFactory Test, Board Rev 3.1\n");
bool ok = true;
unsigned char maj = HW_REV_MAJOR;
@@ -350,8 +137,8 @@ main(void)
puts("SD OK\n");
else {
puts("SD FAIL\n");
- hal_finish();
- return 0;
+ //hal_finish();
+ //return 0;
}
if(test_ram())
puts("RAM OK\n");
@@ -364,4 +151,12 @@ main(void)
print_mac_addr(ethernet_mac_addr()->addr);
newline();
+ clocks_mimo_config(MC_WE_LOCK_TO_SMA);
+
+ while (!clocks_lock_detect()) {
+ puts("No Lock");
+ mdelay(1000);
+ }
+ puts("Clock Locked\n");
+
}
diff --git a/usrp2/firmware/apps/burnrev40.c b/usrp2/firmware/apps/burnrev40.c
index 719795933..5197f5358 100644
--- a/usrp2/firmware/apps/burnrev40.c
+++ b/usrp2/firmware/apps/burnrev40.c
@@ -39,6 +39,7 @@
#include <usrp2_i2c_addr.h>
#include <clocks.h>
#include "sd.h"
+#include "mdelay.h"
#define HW_REV_MAJOR 4
#define HW_REV_MINOR 0
@@ -150,4 +151,12 @@ main(void)
print_mac_addr(ethernet_mac_addr()->addr);
newline();
+ clocks_mimo_config(MC_WE_LOCK_TO_SMA);
+
+ while (!clocks_lock_detect()) {
+ puts("No Lock");
+ mdelay(1000);
+ }
+ puts("Clock Locked\n");
+
}
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